Compilation for compact power-gating controls

You, Yi-Ping; Huang, Chung-Wen; Lee, Jenq Kuen

doi:10.1145/1278349.1278364

Cited by 17 publications

(11 citation statements)

References 29 publications

(46 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Hardware exceeding the estimated parallelism is shut down via power gating. You et al [2006You et al [ , 2007 proposed an instruction scheduling algorithm to reduce power-gating overhead. Their proposed algorithm, called "sink-and-hoist," traverses the control flow graph to estimate the lifetime of functional units.…”

Section: Compiler-directed Power-gating Controlmentioning

confidence: 99%

“…To cope with the increasing leakage power, Multiple Threshold-Voltage CMOS (MTCMOS) power-gating technologies are proposed [Shin et al 2010]. Various researchers have proposed compiler-assisted power-gating control to reduce the power dissipation of instruction-level parallel processors Wang et al 2010;You et al 2006You et al , 2007. Although power reduction on functional units is widely discussed, we focus on reducing the power dissipated in register files by means of power gating.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Deadline-Constrained Clustered Scheduling for VLIW Architectures using Power-Gated Register Files

Liang

Zhang

2014

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

Designing energy-efficient Digital Signal Processor (DSP) cores has become a key concern in embedded systems development. This paper proposes an energy-proportional computing scheme for Very Long Instruction Word (VLIW) architectures. To make the processor power scales with adapted parallelism, we propose incorporating distributed Power-Gated Register Files (PGRF) into VLIW to achieve a PGRF-VLIW architecture. For energy efficiency, we also propose an instruction scheduling algorithm called the Deadline-Constrained Clustered Scheduling (DCCS) algorithm. The algorithm clusters the data dependence graph to reduce data transfer energy and makes optimal use of low-powered local registers for tree-structured data dependence graphs. The results of evaluations conducted using the MiBench and DSPstone benchmark suites substantiate the expected power saving and scaling effects. . 2014. Deadline-constrained clustered scheduling for VLIW architectures using power-gated register files. ACM Trans.

show abstract

Section: Compiler-directed Power-gating Controlmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Deadline-Constrained Clustered Scheduling for VLIW Architectures using Power-Gated Register Files

Liang

Zhang

2014

ACM Trans. Archit. Code Optim.

View full text Add to dashboard Cite

show abstract

“…For leakage power optimization, the integration of both architectural and compiler power-gating schemes are presented in [31][32][33]. Also the Sink-N-Hoist framework for generating balanced compiler power-gating instructions is introduced in [5]. These works above are targeting at instruction level for the design of compiler techniques for low power.…”

Section: Related Workmentioning

confidence: 99%

“…As the application software is associated with early decisions of design, power optimization in the software layer will also give the opportunity for design option explorations. Early work in power optimizations from compiler viewpoints include reducing power consumption via software arrangements at instruction-level to reduce power consumption [2][3][4], compiler supports for instruction utilization analysis for leakage power reduction [2], software re-arrangements to utilize the value locality of registers [3], the scheduling of VLIW instructions to reduce the power consumption on the instruction bus [4], power optimizations with Sink-NHoist schemes [5], and energy aware scheduling for parallel security processors [6].…”

Section: Introductionmentioning

confidence: 99%

Compilers for Low Power with Design Patterns on Embedded Multicore Systems

Lin

Kuan

Shih

et al. 2014

J Sign Process Syst

Self Cite

View full text Add to dashboard Cite

Minimization of power dissipation can be considered at algorithmic, compiler, architectural, logic, and circuit level. Recent research trends for multicore programming models have come to the direction that parallel design patterns can be a solution to develop multicore applications. As parallel design patterns are with regularity, we view this as a great opportunity to exploit power optimizations in the software layer. In this paper, we investigate compilers for low power with parallel design patterns on embedded multicore systems. We evaluate four major parallel design patterns, Pipe and Filter, MapReduce with Iterator, Puppeteer, and Bulk Synchronous Parallel (BSP) Model. Our work attempts to devise power optimization schemes in compilers by exploiting the opportunities of the recurring patterns of embedded multicore programs. The proposed optimization schemes are rate-based optimization for Pipe and Filter pattern , early-exit power optimization for MapReduce with Iterator pattern, power aware mapping algorithm for Puppeteer pattern, and multi-phases power gating scheme for BSP pattern. In our experiments, real world multicore applications are evaluated on a multicore power simulator. Significant power reductions are observed from the experimental results. Therefore, we present a direction for power optimizations that one can further

show abstract

“…These approaches are performance-oriented optimizations, with any reduction in energy consumption merely representing a by-product. Recent studies have attempted to reduce the leakage power consumption using integrated architecture and compiler power-gating mechanisms [You et al 2002[You et al , 2005[You et al , 2006[You et al , 2007Rele et al 2002;Dropsho et al 2002;Yang et al 2002;Zhang et al 2003]. These approaches involve compilers inserting instructions into programs to shut down and wake up components whenever appropriate, based on a dataflow or profiling analysis.…”

Section: Related Workmentioning

confidence: 99%

Energy-aware code motion for GPU shader processors

You

Wang

2013

ACM Trans. Embed. Comput. Syst.

Self Cite

View full text Add to dashboard Cite

Graphics processing units (GPUs) are now being widely adopted in system-on-a-chip designs, and they are often used in embedded systems for manipulating computer graphics or even for general-purpose computation. Energy management is of concern to both hardware and software designers. In this article, we present an energy-aware code-motion framework for a compiler to generate concentrated accesses to input and output (I/O) buffers inside a GPU. Our solution attempts to gather the I/O buffer accesses into clusters, thereby extending the time period during which the I/O buffers are clock or power gated. We performed experiments in which the energy consumption was simulated by incorporating our compiler-analysis and code-motion framework into an in-house compiler tool. The experimental results demonstrated that our mechanisms were effective in reducing the energy consumption of the shader processor by an average of 13.1% and decreasing the energy-delay product by 2.2%.

show abstract

Compilation for compact power-gating controls

Cited by 17 publications

References 29 publications

Deadline-Constrained Clustered Scheduling for VLIW Architectures using Power-Gated Register Files

Deadline-Constrained Clustered Scheduling for VLIW Architectures using Power-Gated Register Files

Compilers for Low Power with Design Patterns on Embedded Multicore Systems

Energy-aware code motion for GPU shader processors

Contact Info

Product

Resources

About