Compensating Pixel Circuit Driving AMOLED Display With a-IGZO TFTs

We demonstrated the high performance back-channel-etched (BCE) amorphous-InGaZnO (a-IGZO) thin-film transistor (TFT) circuits. The TFTs exhibited the field-effect mobility, turn-on voltage and subthreshold swing of 18 cm 2 /V•s, -0.1 V, and 258 mV/dec, respectively. The oscillation frequency of an 11 stages ring-oscillator is ~334.1 kHz, at VDD = 20 V. The 320 stages 11T2C shift-register operated well up to the last stage with rising and falling times of 950 and 690 ns, respectively. Good performance is attributed to damage-free back channel wet etch process and small overlap capacitance between the gate and source/drain electrodes.

Section: Introductionmentioning

confidence: 99%

P‐7: High Speed a‐IGZO TFT‐based Gate Driver by using Back Channel Etched Structure

Um¹,

Mativenga²,

Geng³

et al. 2014

“…IGZO TFTs are promising candidates for display applications, such as in LCD, OLED, QLED, etc. [1][2][3][4].…”

Section: Introductionmentioning

confidence: 99%

15.3: Asymmetric Conductance of Oxide Thin‐Film Transistors Induced by Top‐Gate Effect of Drain Overlap Capacitance

Huang¹,

Zhang²,

Dai³

et al. 2019

“…In recent years, amorphous oxide semiconductor thin film transistors (AOS-TFTs), especially a-IGZO TFTs have been extensively investigated for application in the next generation displays like active-matrix organic light-emitting diode displays (AMOLEDs) due to the advantages of high mobility, low processing temperature and large area uniformity [1], [2].…”

Section: Introductionmentioning

confidence: 99%

P‐1.6: Effect of Deposition Condition of Passivation Layer on the Performance of Self‐Aligned Top‐Gate a‐IGZO TFTs

Zhang

Yang

Zhang

et al. 2018

In this paper, we fabricated self‐aligned top‐gate (SATG) amorphous indium‐gallium‐zinc‐oxide (a‐IGZO) thin‐film transistors (TFTs). The conductive source/drain regions were formed by hydrogen incorporation during the deposition of SiOx or SiNx passivation layer using plasma‐enhanced chemical vapor deposition (PECVD). The effect of passivation layer deposition condition on the electrical performance of self‐aligned top‐gate a‐IGZO TFTs was investigated. It was shown that the source‐drain parasitic resistance (Rsd) was effectively reduced during the deposition of SiNx passivation layer than SiOx. However, as the deposition temperature of SiNx passivation layer increased, hydrogen lateral diffusion into channel region resulted in the shrinkage of effective channel length and the deterioration of electrical performance of short‐channel device.