Comparison of SOI and Partial-SOI LDMOSFETs Using Electrical–Thermal–Stress Coupled-Field Effect

Tan, Cher Ming; Huang, Guangyu

doi:10.1109/ted.2011.2162588

Cited by 4 publications

(2 citation statements)

References 20 publications

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“…To enhance breakdown voltage (BV), an LVD profile is inserted into thin-film SOI LDMOS [3]. Meanwhile, partial silicon-on-insulator (PSOI) technology [4][5][6] has been reported to solve the SHE problem because the silicon window underneath the source side or drain side helps heat dissipate into the device substrate. In addition, it is possible to obtain higher BV than the conventional SOI device due to the fact that some voltages are supported by the depletion layer in the substrate.…”

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confidence: 99%

Uniform and linear variable doping ultra‐thin PSOI LDMOS with n‐type buried layer

Qiao

Jiang

et al. 2013

Electron. lett.

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A novel ultra-thin partial silicon-on-insulator (PSOI) LDMOS with n-type buried (n-buried) layer (NBL PSOI LDMOS) is proposed. The new PSOI LDMOS features an n-buried layer underneath the n-type drift (n-drift) region close to the source side, providing a large conductivity region for majority carriers to significantly improve the self-heating effect. A combination of uniform and linear variable doping (LVD) profile with highly initial concentration is utilised in the n-drift region, which alleviates the inherent tradeoff between specific on-resistance (R on,sp ) and breakdown voltage (BV), as well as achieving low power dissipation. With a 60-µm n-drift region length, the NBL PSOI LDMOS obtains a high BV of 940 V with a low maximum temperature (T max ) of 327 K at a power (P) of 1 mW/μm, which is reduced by around 56 K in comparison to the conventional SOI LDMOS using an LVD profile for the n-drift region (LVD SOI LDMOS). Moreover, R on,sp of the NBL PSOI LDMOS is lower than that of the LVD SOI LDMOS for a wide range of BV from 400 to 900 V.Introduction: SOI technology is of great benefit to high-voltage lateral devices because of the ideal dielectric isolation, low leakage current and high speed [1]. However, SOI power devices suffer from the self-heating effect (SHE) [2], which results in threshold voltage shift, deteriorating reliability and low carrier mobility. Moreover, the thickness of the buried oxide is a limiting factor for SOI power devices in high-voltage applications. To enhance breakdown voltage (BV), an LVD profile is inserted into thin-film SOI LDMOS [3]. Meanwhile, partial silicon-on-insulator (PSOI) technology [4-6] has been reported to solve the SHE problem because the silicon window underneath the source side or drain side helps heat dissipate into the device substrate. In addition, it is possible to obtain higher BV than the conventional SOI device due to the fact that some voltages are supported by the depletion layer in the substrate. A novel ultra-thin NBL PSOI LDMOS using a uniform and linear variable doping (ULVD) profile with highly initial concentration is presented in this Letter, which achieves lower SHE and lower R on,sp with higher BV than the conventional LVD SOI LDMOS. The influence of the device parameters on the surface temperature, T max , R on,sp and BV are analysed by twodimensional device simulator MEDICI.

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confidence: 99%

Uniform and linear variable doping ultra‐thin PSOI LDMOS with n‐type buried layer

Qiao

Jiang

et al. 2013

Electron. lett.

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“…The PSOI SJ-LDMOSFET was reported as a preferred solution to conventional SOI (C-SOI) SJ-LDMOSFETs [75][76][77][78][79][80]. The silicon opening in this device architecture serves as a thermal window for heat transfer from the active SOI layer to the p-substrate thereby reducing the self-heating effect [81,82], but also enhancing uniform distribution of electric field in the drift region [83,84].…”

Section: Partial Silicon On Insulator (Psoi) Sj-ldmosfetmentioning

confidence: 99%

Design and Scaling of Lateral Super-Junction Multi-Gate MOSFET by 3-D TCAD Simulations

Adenekan¹

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Bless the Lord, O my soul: and all that is within me, bless his holy name. I give all glory to the Almighty God for the successful completion of the research programme, without HIM I am nothing. Many thanks to my supervisor, Prof. Karol Kalna for his valuable guidance and support throughout my research programme at Swansea University. Also, I would like to thank my second supervisor, Dr. Paul M. Holland, for his support and insightful discussions all through the research work. I thank my colleagues, most especially John Macaulay and members of the research group for making the research experience interesting and educative. Many thanks to the Federal Government of Nigeria and the Management of Moshood Abiola Polytechnic, Abeokuta for the opportunity availed me to undergo my research programme in Swansea University, UK. I thank especially Samson and Taiwo Folorunso, Waliu Okunade, Abiodun Olubanjo, Simeon Afonja, Gbekeleoluwa, auntie Bimple, auntie Iyabo, Taiwo and Tobi Okeneye; for all the support they have given to me throughout my period of studying in UK. I thank all my friends and siblings for your pleasant and encouraging words in the course of the research. I am very thankful to Akeem and Sola Durotoye, for your extremely support both morally and financially. My thanks also go to my parents, and my in-laws who supported me morally and spiritually. To my Kids, a big thank you for your sacrifices without complaint and keeping the flags flying while I pursued further education. Last of all, I would like to thank my wife, Oyeyinka, she has always been a blessing and a strong pillar of support. Many thanks for the words of courage during those hard moments of the research work; most importantly you freed me from family responsibilities so that I can achieve my desire goal. v To my wife and my jewel of inestimable value, Oyeyinka and my lovely kids, Oluwadarasimi, Oluwadamisi and Oluwadabira.

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A novel SOI LDMOS with substrate field plate and variable-k dielectric buried layer

Zhang

et al. 2018

Results in Physics

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Comparison of SOI and Partial-SOI LDMOSFETs Using Electrical–Thermal–Stress Coupled-Field Effect

Cited by 4 publications

References 20 publications

Uniform and linear variable doping ultra‐thin PSOI LDMOS with n‐type buried layer

Uniform and linear variable doping ultra‐thin PSOI LDMOS with n‐type buried layer

Design and Scaling of Lateral Super-Junction Multi-Gate MOSFET by 3-D TCAD Simulations

A novel SOI LDMOS with substrate field plate and variable-k dielectric buried layer

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