Uniform and linear variable doping ultra‐thin PSOI LDMOS with n‐type buried layer

Abstract

A novel ultra-thin partial silicon-on-insulator (PSOI) LDMOS with n-type buried (n-buried) layer (NBL PSOI LDMOS) is proposed. The new PSOI LDMOS features an n-buried layer underneath the n-type drift (n-drift) region close to the source side, providing a large conductivity region for majority carriers to significantly improve the self-heating effect. A combination of uniform and linear variable doping (LVD) profile with highly initial concentration is utilised in the n-drift region, which alleviates the inherent tradeoff between specific on-resistance (R on,sp ) and breakdown voltage (BV), as well as achieving low power dissipation. With a 60-µm n-drift region length, the NBL PSOI LDMOS obtains a high BV of 940 V with a low maximum temperature (T max ) of 327 K at a power (P) of 1 mW/μm, which is reduced by around 56 K in comparison to the conventional SOI LDMOS using an LVD profile for the n-drift region (LVD SOI LDMOS). Moreover, R on,sp of the NBL PSOI LDMOS is lower than that of the LVD SOI LDMOS for a wide range of BV from 400 to 900 V.Introduction: SOI technology is of great benefit to high-voltage lateral devices because of the ideal dielectric isolation, low leakage current and high speed [1]. However, SOI power devices suffer from the self-heating effect (SHE) [2], which results in threshold voltage shift, deteriorating reliability and low carrier mobility. Moreover, the thickness of the buried oxide is a limiting factor for SOI power devices in high-voltage applications. To enhance breakdown voltage (BV), an LVD profile is inserted into thin-film SOI LDMOS [3]. Meanwhile, partial silicon-on-insulator (PSOI) technology [4-6] has been reported to solve the SHE problem because the silicon window underneath the source side or drain side helps heat dissipate into the device substrate. In addition, it is possible to obtain higher BV than the conventional SOI device due to the fact that some voltages are supported by the depletion layer in the substrate. A novel ultra-thin NBL PSOI LDMOS using a uniform and linear variable doping (ULVD) profile with highly initial concentration is presented in this Letter, which achieves lower SHE and lower R on,sp with higher BV than the conventional LVD SOI LDMOS. The influence of the device parameters on the surface temperature, T max , R on,sp and BV are analysed by twodimensional device simulator MEDICI.

Analytical model for silicon-on-insulator lateral high-voltage devices using variation of lateral thickness technique

“…Varied lateral doping (VLD) technology is effective for improving the breakdown voltage by providing an ideal uniform lateral electric field. [16][17][18][19][20] However, the doping concentration near the source side of the drift region in VLD devices must be kept low, thereby leading to a high specific on-resistance. To overcome the drawback of RESURF and VLD devices, variation of lateral thickness (VLT) technology was proposed.…”

Improving Breakdown Voltage for a Novel SOI LDMOS with a Lateral Variable Doping Profile on the Top Interface of the Buried Oxide Layer

“…A submicron thin film SOI LDMOS with the variable doping profile and numerical modeling of linear doping profiles were proposed in 1996 and 1999, respectively [5,6]. After 2000, several new SOI devices structures with linear doping profile were proposed [7][8][9][10][11].…”

Low Specific On-resistance SOI LDMOS Device with P+P-top Layer in the Drift Region

“…One of the main issues when designing power LDMOS is the trade-off between the breakdown voltage (BV) and specific on-resistance (R sp ) [2]. The REduce SURface Field (RESURF) technique is the most widely used method for designing lateral high voltage and low onresistance MOS devices [3,4], but Single RESURF (S-RESURF) technique must ensure a low drift region concentration to make the epitaxial layer deplete completely, otherwise the high drift concentration will lead to the P well N drift junction electric field premature reaching the critical electric field of silicon, thus reducing the breakdown voltage [5,6]. Moreover, the low drift concentration will also increase the specific onresistance [7].…”