Comparison of Recently Developed Single-Bit All-Digital Frequency Synthesizers in Terms of Hardware Complexity and Performance

Basetas, Charis; Temenos, Nikos; Sotiriadis, Paul P.

doi:10.1109/iscas.2018.8351798

Cited by 3 publications

(3 citation statements)

References 10 publications

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“…The SDM's maximum operating frequency f s corresponds to the register's one and, as expected, determines the input signal's maximum operating frequency f B that the architecture is able to process. Optionally, a dithering sequence can be employed to further decrease the SDM's output noise floor [32][33][34].…”

Section: Sdm Encodingmentioning

confidence: 99%

“…A well-known method to reduce the noise floor and improve the spectral characteristics of a quantized signal is to use sigma-delta modulators (SDMs) [32][33][34]. They convert a high-resolution signal (several bits) into a lower-bit one by employing the technique of oversampling; the input signal is sampled at a frequency much higher than the Nyquist, thus reducing the noise in the desired frequency band of interest.…”

Section: Introductionmentioning

confidence: 99%

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Efficient Stochastic Computing FIR Filtering Using Sigma-Delta Modulated Signals

2022

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This work presents a soft-filtering digital signal processing architecture based on sigma-delta modulators and stochastic computing. A sigma-delta modulator converts the input high-resolution signal to a single-bit stream enabling filtering structures to be realized using stochastic computing’s negligible-area multipliers. Simulation in the spectral domain demonstrates the filter’s proper operation and its roll-off behavior, as well as the signal-to-noise ratio improvement using the sigma-delta modulator, compared to typical stochastic computing filter realizations. The proposed architecture’s hardware advantages are showcased with synthesis results for two FIR filters using FPGA and synopsys tools, while comparisons with standard stochastic computing-based hardware realizations, as well as with conventional binary ones, demonstrate its efficacy.

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Section: Sdm Encodingmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Efficient Stochastic Computing FIR Filtering Using Sigma-Delta Modulated Signals

2022

Self Cite

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“…3 together with sub-blocks for amplitude tracking and noise shaping. Introducing a ∆Σ modulator is a well established means reduce hardware complexity for multiplication as the ±1 single bit-stream implies that the coefficients (f & k) can be directly accumulated accordingly [14]. This is particularly appropriate here because the typical clock speed will be at a substantially higher frequency than the signal bandwidth of interest.…”

Section: ∆σ 2 Type Ddws Corementioning

confidence: 99%

Direct Digital Wavelet Synthesis for Embedded Biomedical Microsystems

Leene

Constandinou

2018

2018 IEEE Biomedical Circuits and Systems Conference (BioCAS)

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This paper presents a compact direct digital wavelet synthesizer for extracting phase and amplitude data from cortical recordings using a feed-forward recurrent digital oscillator. These measurements are essential for accurately decoding localfield-potentials in selected frequency bands. Current systems extensively to rely large digital cores to efficiently perform Fourier or wavelet transforms which is not viable for many implants. The proposed system dynamically controls oscillation to generate frequency selective quadrature wavelets instead of using memory intensive sinusoid/cordic look-up-tables while retaining robust digital operation. A MachXO3LF Lattice FPGA is used to present the results for a 16 bit implementation. This configuration requires 401 registers combined with 283 logic elements and also accommodates real-time reconfigurability to allow ultra-lowpower sensors to perform spectroscopy with high-fidelity.

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A Novel Stochastic Polar Architecture for All-Digital Transmission

Andriakopoulos

Papachatzopoulos

Paliouras

2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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A novel architecture of an all-digital transmitter is proposed in this paper, introducing stochastic computation to a single-bit polar topology. The proposed architecture exploits the benefits of stochastic computing to simplify the design of an alldigital transmitter and minimize hardware complexity. Complexity reduction is achieved by implementing a digital oscillator as a cosine function in the stochastic domain instead of resorting to LUT-based or CORDIC-based implementations. An evaluation of the introduced all-digital polar architecture shows that the power spectral density of the transmitted passband signal is similar to that of a conventional transmitter. Synthesis of the proposed stochastic-enabled transmitter at a 28-nm FDSOI technology node reveals its minimal complexity requirements and 87.13% area reduction compared to conventional implementations.

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Comparison of Recently Developed Single-Bit All-Digital Frequency Synthesizers in Terms of Hardware Complexity and Performance

Cited by 3 publications

References 10 publications

Efficient Stochastic Computing FIR Filtering Using Sigma-Delta Modulated Signals

Efficient Stochastic Computing FIR Filtering Using Sigma-Delta Modulated Signals

Direct Digital Wavelet Synthesis for Embedded Biomedical Microsystems

A Novel Stochastic Polar Architecture for All-Digital Transmission

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