Comparison of quasi-/pseudo-floating gate techniques

Abstract

Recently, the quasi-or pseudo-floating gate (QFG) technique has been suggested by several authors to implement many of the functions of the widely used floatinggate MOS transistor technique by using ultra-high resistances to isolate a floating node. Several different ways have been suggested to implement these quasi-infinite resistors (QIRs). In this paper, several basic QIR structures are analyzed and compared, and three sources of error, dc offset, signal distortion, and signal-dependent offset, are defined. Then, through simulations and experiments, the suitability of several QIR implementations for use in various applications are compared. One implementation is shown to minimize dc offset, but voltage swing is limited to less than 0.7 V PP . Configurations using parallel connections of QIRs improve signal distortion and signal-dependent offset, but still suffer from dc offset and limited voltage swing. Series-connected QIR structures allow increased voltage swings, but typically lead to hard-to-predict offsets of up a few hundred mV because of well-substrate leakage currents. Other circuits are also analyzed.

An improved common-mode feedback loop for the differential-difference amplifier

“…For a comparative analysis, it should be noted that the special processes as the FinFET [14], or the floating gate technology [15] as also the bulk-driven technique [7,16], require a very accurate design for a reliable operation [17][18][19][20]. Therefore, some considerations related to standard CMOS design and the clock phases minimization, makes AF-SHA among the most efficient architectures also compared to FOM of the SHA-less analog-to-digital converters (ADCs) [21,22].…”