Comparison of NMOS and PMOS Input Driving Dynamic Comparator in 45nm Technology

Abstract

A comparison of NMOS and PMOS input driving dynamic comparator is carried out in 45nm technology. NMOS driving dynamic comparator shows lesser delay and consumes less power as compared to PMOS driving comparator. The advantage of the later is the noise immunity at higher frequencies. The normalized energy-noise-delay-product (ENDP) for NMOS dynamic comparator and PMOS dynamic comparator is 2.08 and 4.48, respectively.

Fast physical reservoir computing, achieved with nonlinear interfered spin waves

“…Thus, the electric power consumption estimated under the condition without the accumulation is much lower than those networks (i.e. 1.26 µJ (this study) < 34.4 µJ [58] < 936 µJ [59]). The reservoir network and peripheral circuit implemented on the terminal device can be designed based on fine devices such as magnon transistors, operating with a meager energy consumption of 10 −18 J (≪ CMOS of 10 −16 J) [50] and readout layer consisting of magnetic tunnel junction array (approximately 50 × 10 −15 J) [60].…”

“…Echo state networks and liquid state machines, the recurrent neural networks implemented in complementary metal oxide semiconductor (CMOS) circuits, utilize memristor arrays [58,59]. The electrical power consumption of the echo state network and the liquid state machine are 34.4 and 936 µJ, respectively [58,59]. Thus, the electric power consumption estimated under the condition without the accumulation is much lower than those networks (i.e.…”

“…For a 2-input adder, 11 NMOS and 11 PMOS transistors (i.e., 22 in total) are used each, and the area of the adder for 500 inputs corresponding to 500 integrations is 250 × 11 × (4S 2 + 8S 2 ) = 13.94 µm 2 [58]. An analog-to-digital converter (ADC) consists of 2 n -1 comparators depending on the number of bits n. The area of an n-bit ADC is represented by (2 n -1) × 52S 2 , which is approximately 56-224 µm 2 (n = 8-10 bits) [59]. A 4ch DEMUX consists of 14 NMOS and 14 PMOS, and the area of a DEMUX with 100 channels is 14 × (4S 2 + 8S 2 ) × 25 = 17.8 µm 2 .…”

“…The power consumption of the memristor is 5.05 fJ, and from 100 nodes and the length of output vectors, the power consumption of the memristor crossbar array is 5.05 fJ × 100 × 100 = 50.5 pJ. For other CMOS circuits, the power consumption of the adder is 0.176 fJ [58], the power consumption of the ADC is 151 nJ [59]. Since the power consumption of the physical reservoir is 628 µJ (500 times integration) and 1.26 µJ without integration, the power consumption of the memristor crossbar array and typical peripheral CMOS circuitry is sufficiently small compared to that of the physical reservoir.…”

Construction of pMos Logic based Low Power High Speed Comparator Compare with nMos Logic

“…20 different values of length of transistor were taken for the analysis. Same values of length were taken for both the groups (S. Hussain, Kumar, and Trivedi 2021). In the existing system, N-type metal-oxide-semiconductor logic uses n-type MOSFETs to implement logic gates and other digital circuits.…”