Comparison of latch-up in p- and n-well CMOS circuits

Takacs, D.; Harter, J.; Jacobs, E.P.; Werner, Christoph; Schwabe, Ulrich; Winnerl, J.; Lange, E.

doi:10.1109/iedm.1983.190466

Cited by 20 publications

(5 citation statements)

References 0 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…However, the values were found t o have very little quantitative effect on the latch-up characteristics [53], [54]; in fact the strong resistance temperature dependence (a factor of 7 has been measured for temperatures ranging from 150 K to 400 K [44] causes a propotional increase in the current required to forward bias the BJT's emitter-base junctions, thus effectively changing the bipolar bias configuration at the triggering point.…”

Section: Effects O F Temperaturementioning

confidence: 99%

Latch‐up in CMOS circuits: A review

Sangiorgi¹

1990

Trans Emerging Tel Tech

View full text Add to dashboard Cite

In CMOS technologies, rapidly becoming the most important ones for VLSI microelectronics, the inherent phenomenon of latch‐up, represents one of the most serious limitations for further dimension scaling in the deep sub‐micron range. For this reason latch‐up has attracted a lot of attention in the last decade and a deep understanding of its essential features has been achieved, although a few specific problems are still to be satisfactorily solved.

show abstract

Section: Effects O F Temperaturementioning

confidence: 99%

Latch‐up in CMOS circuits: A review

Sangiorgi¹

1990

Trans Emerging Tel Tech

View full text Add to dashboard Cite

show abstract

“…In the late 1980s and early 1990s new semiconductor processes further enhanced the CMOS latchup robustness of the mainstream CMOS technologies [9][10][11][12][13][14][15][16][17][18][19][20]. In CMOS technology, semiconductor process solutions were integrated to improve the CMOS latchup issue.…”

Section: Introductionmentioning

confidence: 99%

A review of CMOS latchup and electrostatic discharge (ESD) in bipolar complimentary MOSFET (BiCMOS) Silicon Germanium technologies: Part II—Latchup

Voldman¹

2005

Microelectronics Reliability

View full text Add to dashboard Cite

“…For the calculation of boron concentration in the epi.. taxial wafer, the boron concentration at a position in the epitaxial film sufficiently far from the interface between the epitaxial film and the substrate at time t, C,, is fixed to the value measured by secondary ion mass spectrometry (SIMS), CObS, as shown in Fig. 2b = C0, [4] Although Eq. 1 can be analytically solved for evaporation and diffusion from the substrate to the epitaxial layer individually, the epitaxial growth must be performed immediately after the prebaking process in which a native oxide film is removed from the substrate surface.…”

Section: Introductionmentioning

confidence: 99%

Effect of Transport Phenomena on Boron Concentration Profiles in Silicon Epitaxial Wafers

Habuka

Mayusumi

Tsunoda

et al. 1996

J. Electrochem. Soc.

View full text Add to dashboard Cite

The boron concentration profile in silicon epitaxial wafers grown under atmospheric pressure was investigated in two types of epitaxial reactors. Transport phenomena are studied both by numerical calculations or by a gas flow visualization technique. The difference between the measured boron concentration profile and the calculated one using Fick's law was assumed to be due to autodoping. In epitaxial wafers grown at temperatures lower than 1273 K on a p-type substrate in a single-wafer horizontal reactor which has no recirculation of gas, the boron concentration profile changed abruptly at the interface between the epitaxial film and the substrate since the profile is formed only due to solid-state diffusion. In contrast, in a pancake reactor having large recirculation of gas, a gradual change in the boron concentration profile was observed due to autodoping via the gas phase. In conclusion, large amounts of recirculation of gas in an epitaxial reactor should be avoided to obtain an abrupt boron concentration profile.

show abstract

Comparison of latch-up in p- and n-well CMOS circuits

Cited by 20 publications

References 0 publications

Latch‐up in CMOS circuits: A review

Latch‐up in CMOS circuits: A review

A review of CMOS latchup and electrostatic discharge (ESD) in bipolar complimentary MOSFET (BiCMOS) Silicon Germanium technologies: Part II—Latchup

Effect of Transport Phenomena on Boron Concentration Profiles in Silicon Epitaxial Wafers

Contact Info

Product

Resources

About