Comparison of FPGA and Microcontroller Implementations of an Innovative Method for Error Magnitude Evaluation in Reed–Solomon Codes

Abstract

Reed-Solomon (RS) codes are one of the most used solutions for error correction logic in data communications. RS decoders are composed of several blocks: among them, many efforts have been made to optimize the error magnitude evaluation module. This paper aims to assess the performance of an innovative algorithm introduced in the literature by Lu et al. under different systems configurations and hardware platforms. Several configurations of the encoded message chosen between those typically used in different applications have been designed to be run on an FPGA (field programmable gate array) device and an MCU (microcontroller unit). The performances have been evaluated in terms of resource usage and output delay for the FPGA and in terms of code execution time for the MCU. As a benchmark in the analysis, the well-established Forney's method is exploited: it has been implemented in the same configurations and on the same hardware platforms for a proper comparison. The results show that the theoretical finding are fully confirmed only in the MCU implementation, while on FPGA, the choice of one method with respect to the other depends on the optimization feature (i.e., time or area) that has been decided as a preference in the specific application.Electronics 2020, 9, 89 2 of 15 ECCs can correct up to one error in the message and are characterized by low parity information, which makes them suitable for applications requiring high data rates, but low error occurrence. To improve Hamming codes, Bose-Chaudhuri-Hocquenghem (BCH) codes were presented in the works of [9][10][11]. They solve the limitation of the maximum correctable errors by introducing Galois Fields [12]. By exploiting the multiplication, the addition, and the inversion defined in the field, the system can be configured to correct the desired amount of errors in the message by increasing the parity information appended to the message itself. A subset of BCH codes are Reed-Solomon (RS) codes [13], which ease the implementation in binary encoded messages. RS codes are among the most implemented solutions in a wide set of areas, such as data storage, bar and QR (quick response) codes, space and TV transmission, and so on [14][15][16][17].As all communication systems, RS ECCs are composed of an encoder at the sender side and a decoder at the receiver side. Most of the works in the literature [18][19][20] focus on the decoder part, as it holds the most complex operations. Several approaches have been proposed to improve the performance of the decoder [21,22]. Among them, many research works focus on the optimization of error magnitude evaluation [23][24][25]. A traditional implementation exploits the Forney method [23]. Komo and Joiner proposed an iterative algorithm in the work of [24] based on a Vandermonde matrix, which results in an improvement of the processing speed of about 2.8 times compared with the Forney method. Then, an innovative method has been proposed by Lu et al. [25], allowing the same result to be obtained with less system complexity and...

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“…This advantage makes RS code widely used in information transmission. As a message processing algorithm, RS code has time and space advantages when applied to FPGA and MCU [9]. This is also due to the flexibility of the RS code, which allows it to meet various usage scenarios by adjusting the code rate.…”

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“…The designed divider is also able to handle the special case in which the most significant symbol of the syndrome is zero. Errors positions and values evaluation has been carried out with well-established Chien [25] and Forney [15,26] methods respectively. The whole designed architecture is, also in this case, pipe-lined.…”

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“…These power controls generally lack precision and do not work in real time; to overcome these limitations, different solutions relying on FPGA (Field Programmable Gate Array)-implemented algorithms can be exploited [5]. In the last few years, the application of FPGA devices has increased exponentially in a wide variety of fields, such as: digital signal processing [6][7][8][9][10], data processing [11,12], bioinformatics [13,14] and power electronics [15][16][17]. Among the applications based on FPGAs that recently have been applied to the smart grid field, MPC (Model Predictive Control) has particular importance [18][19][20].…”