Comparison of Fin-Edge Roughness and Metal Grain Work Function Variability in InGaAs and Si FinFETs

Abstract

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Impact of Gate Edge Roughness Variability on FinFET and Gate-All-Around Nanowire FET

“…3 (bottom). As previously reported for LER [26], GER variability will increase with the RMS. We obtain maximum variability values at a RMS value of 1.0 nm, where σV T and σlog 10 (I OFF ) are 34% and 18% larger for the FinFET than for the GAA NW FET, respectively.…”

Scaling/LER study of Si GAA nanowire FET using 3D finite element Monte Carlo simulations

“…12 shows the OFF-current (I OFF,high ) versus the threshold voltages ( The 22 nm gate length GAA NW shows smaller variations for the four figures of merit at low and high drain biases than the ones observed in the 10 nm gate length GAA NW (see Fig. 8) as expected but the increase in the device variability is relatively small when comparing correlation coefficients (CC) [6], [7]. This demonstrates that the GAA NW FETs are strong candidates for future generation of digital transistors delivering large on-current required in a circuit design accompanied by a well controlled device variability.…”

Impact of Cross-Sectional Shape on 10-nm Gate Length InGaAs FinFET Performance and Variability

“…With respect to the MGG, we have limited the study to devices with an average grain size (GS) of 7 nm. An in-depth study of the influence of the grain size can be found in [27]. An example of a metal gate profile from the grain size of 7 nm is shown in Fig.…”

“…When studying the influence of the LER, we have limited the analysis to devices with a correlation length (CL) of 10 nm and a root mean square (RMS) height of 0.8 nm, considering uncorrelated fin edge roughness variations. These values were chosen to represent the ones observed in experimental devices [27]. Fig.…”