Comparison Between High-Holding-Voltage SCR and Stacked Low-Voltage Devices for ESD Protection in High-Voltage Applications

Dai, Chia-Tsen; Ker, Ming‐Dou

doi:10.1109/ted.2017.2785121

Cited by 27 publications

(7 citation statements)

References 7 publications

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“…However, most ESD protection structures fabricated in the SOI BCD process are designed for high-voltage applications [16][17][18], while the protection structures for a lowvoltage applications' process are rarely discussed. Embedding a pMOS in DDSCR can reduce V t1 and increase the V h , however, the effect of gate voltage on critical parameters for DDSCR is not investigated in detail.…”

Section: Introductionmentioning

confidence: 99%

The ESD Characteristics of a pMOS-Triggered Bidirectional SCR in SOI BCD Technology

Cai

Zeng

et al. 2022

Electronics

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In this work, the electrostatic discharge (ESD) characteristics of a pMOS-triggered bidirectional silicon-controlled rectifier (PTBSCR) that was fabricated in a 0.18 μm silicon-on-insulator (SOI) bipolar-CMOS-DMOS (BCD) process, is investigated. The multi-snapback phenomenon was observed under the transmission line pulsing (TLP) test system. It was found that gate voltage and inserting shallow trench isolation (STI) can significantly affect the trigger voltage and holding voltage. The underlying physical mechanism related to the multi-snapback phenomenon and the effects of gate voltage on the critical parameters was investigated through the experimental results and the assistance of technology computer-aided design (TCAD) simulations. The adjustments of gate voltage and STI on the critical ESD parameters of the device provide an effective design idea for low-voltage ESD protection in the SOI BCD process.

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Section: Introductionmentioning

confidence: 99%

The ESD Characteristics of a pMOS-Triggered Bidirectional SCR in SOI BCD Technology

Cai

Zeng

et al. 2022

Electronics

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“…[13] Dai and Ker found that the Joule-heating effect could dramatically reduce the holding voltage (V h ) of the proposed SCR, and ESD robustness of the proposed SCR device can decrease when a high (V h ) is achieved. [14] Du et al proposed an enhanced bidirectional modified lateral silicon controlled rectifier (EBMLSCR) and evaluated the effect of some critical dimensions of the EBMLSCR on further op-timizing the device performances. [15] Du et al proposed a compact and self-isolated dual directional silicon-controlled rectifier (CSDDSCR) developed in a single N-well, and the holding voltage reversal effect has also been discovered and explained with technology computer aided design (TCAD) simulation.…”

Section: Introductionmentioning

confidence: 99%

New DDSCR structure with high holding voltage for robust ESD applications*

Zhou¹,

Jin²,

Wang³

et al. 2021

Chinese Phys. B

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A novel dual direction silicon-controlled rectifier (DDSCR) with an additional P-type doping and gate (APGDDSCR) is proposed and demonstrated. Compared with the conventional low-voltage trigger DDSCR (LVTDDSCR) that has positive and negative holding voltages of 13.371 V and 14.038 V, respectively, the new DDSCR has high positive and negative holding voltages of 18.781 V and 18.912 V in a single finger device, respectively, and it exhibits suitable enough positive and negative holding voltages of 14.60 V and 14.319 V in a four-finger device for ±12-V application. The failure current of APGDDSCR is almost the same as that of LVT-DDSCR in the single finger device, and the four-finger APGDDSCR can achieve positive and negative human-body model (HBM) protection capabilities of 22.281 kV and 23.45 kV, respectively, under 40-V voltage of core circuit failure, benefitting from the additional structure. The new structure can generate a snapback voltage on gate A to increase the current gain of the parasitic PNP in holding voltage. Thus, a sufficiently high holding voltage increased by the structure can ensure that a multi-finger device can also reach a sufficient holding voltage, it is equivalent to solving the non-uniform triggering problem of multi-finger device. The operating mechanism and the gate voltage are both discussed and verified in two-dimensional (2D) simulation and experiemnt.

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“…Therefore, it cannot provide an efficient output ESD protection alone. In order to optimize the I-V characteristics of the SCR, various methods have been proposed to improve the holding voltage of the SCR for medium-and high-voltage circuit (10 V/12 V/24 V/40 V) ESD protections [3][4][5][6][7][8][9]. However, the above methods will introduce higher turn-on resistance (R on ) and lower effective protection current (I eff ), or even additional fabrication cost.…”

Section: Introductionmentioning

confidence: 99%

A latch-up-free LVTSCR with improved overshoot characteristic for ESD protection in 40 nm CMOS process

Chen

Liu

Guo

et al. 2021

Semicond. Sci. Technol.

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In this paper, a novel robust low-voltage-triggered silicon-controlled rectifier (LVTSCR) with high holding voltage, low trigger voltage, and low overshoot voltage has been proposed for 5 V integrated circuit electrostatic discharge (ESD) protection. The new LVTSCR integrates an extra low-resistance current path by embedding an NMOS transistor into the traditional LVTSCR. This extra current path will divert part of the ESD current, thus resulting in a lower overshoot voltage as well as better quasi-static I–V characteristics in the new structure. As such, the holding voltage of the new LVTSCR has been increased by ∼23%, the quasi-static triggering characteristic has been decreased by ∼8%, and the overshoot voltage has been improved by ∼38%.

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Comparison Between High-Holding-Voltage SCR and Stacked Low-Voltage Devices for ESD Protection in High-Voltage Applications

Cited by 27 publications

References 7 publications

The ESD Characteristics of a pMOS-Triggered Bidirectional SCR in SOI BCD Technology

The ESD Characteristics of a pMOS-Triggered Bidirectional SCR in SOI BCD Technology

New DDSCR structure with high holding voltage for robust ESD applications*

A latch-up-free LVTSCR with improved overshoot characteristic for ESD protection in 40 nm CMOS process

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