Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture

Abstract

With the advent of Networks-on-Chip (NoCs), the interest for mesochronous synchronizers is again on the rise due to the intricacies of skew-controlled chip-wide clock tree distribution. Recently proposed schemes agree on a source synchronous design style with some form of ping-pong buffering to counter timing and metastability concerns. However, the integration issues of such synchronizers in a NoC setting are still largely uncovered. Most schemes are in fact placed between communicating switches, thus neglecting the abrupt increase of buffering resources needed at switch input stages. This paper goes a step forward and aims at deep integration of the synchronizer in the switch architecture, thus merging key tasks such as synchronization, buffering and flow control into a unique architecture block. This paper compares the integrated and the loosely coupled solutions from a performance and area viewpoint, while devoting special attention to their robustness with respect to physical design parameters.

A GALS Network-on-Chip based on rationally-related frequencies

“…It is valid for a null propagation delay through the channel. Tightly coupling interface and switch as proposed in [19] could decrease this latency, but this lies outside the scope of this work. The best-case hop latency is T R ; the average latency can be experimentally determined and depends on the values of N R , N T and the alignment between the clocks [14].…”

“…A solution specifically tailored for 3D NoCs was introduced in [18]. The benefits of tight coupling between synchronizers and switches are discussed in [19]. An 80-tile mesochronous NoC was used as communication backbone in the Intel TeraFLOPS processor [20].…”

StarSync: An extendable standard-cell mesochronous synchronizer

“…Ref. [29] employs the threeelement cyclic buffer mesochronous synchronizer as shown in Fig.4. The architecture comprises two synchronization paths.…”

“…Another mechanism that enables data bursts was described in [30]. Back-Pressure [29] StarSync is compared to previous work in the rightmost column of Table 1. More specifically, the contributions made in this paper include: 1.…”

Latency Minimization using Mesochronous Scheduling in MPSoC Operation

“…In a Worst case scenario, for example, the buffering of such synchronization parameter should be adjusted based on the source and receiver frequency comparison [11]. In addition, the descriptive presence of information for the frequency ratio (such as, the on-chip interconnects works at faster speed than interlinked IP units), coupled with information of performance limitations, can lead to twin high impact specializations [12]. Hence, the dual clock FIFO architecture has a finally large area and power conservation.…”