Comparator-based switched-capacitor circuits for scaled CMOS technologies

Sepke, Todd; Fiorenza, John Kenneth; Sodini, C.G.; Holloway, P.; Lee, Hae-Seung

doi:10.1109/isscc.2006.1696121

Cited by 127 publications

(62 citation statements)

References 3 publications

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“…This is different from the original sampling in [1], where they used the signal from the comparator to sample in the next stage, thus ensuring no problems with charge leakage. The reason for our method was that we believed it would give us increased speed, we wanted our ADC to run at 100 MHz, not 10 MHz as in [1], so we believed that it would be better to use the clock phases to sample, and not the comparator output. This was an error, and as a result we had to run the ADC above 10 MS/s.…”

Section: Sampling Of Stage Outputmentioning

confidence: 99%

“…We just have to make sure that the output voltage is correct when the next stage samples. Back in 2006 an idea was put forth for a new method of implementing switched-capacitor circuits [1]. Instead of an OTA, they used a current source and a comparator, and called it CBSC, that name has later transformed into zero-crossing-based switched-capacitor circuits (ZBSC), but we'll use the original name, CBSC, in this paper, because this work was based on the original publication.…”

Section: Comparator-based Switched-capacitor Circuitsmentioning

confidence: 99%

“…Below 10 MS/s the change in voltage from the ramp stopped, to the output was sampled, became significant. Accordingly, we recommend that others use the comparator signal for sampling in the next stage, as suggested in [1].…”

Section: Sampling Of Stage Outputmentioning

confidence: 99%

“…Methods to compensate for this overshoot exists, in [1,3] they used a dual ramp system, first a fast ramp to estimate the output voltage, then a slow ramp to fine tune the output voltage. Since the ramp was slow the comparator delay caused an insignificant voltage change.…”

Section: Comparator Delay Compensationmentioning

confidence: 99%

“…This presents a challenge because OTAs are the key component in most switched-capacitor circuits, and switched-capacitor circuits are the de facto standard for implementing ADCs. The challenges in nano-scale CMOS has caused a flurry of research into removing the OTA, where one of the research avenues has led to the comparator-based switched-capacitor circuits (CBSC) [1,2]. In this paper we'll present a pipelined ADC based on this technique.…”

Section: Introductionmentioning

confidence: 99%

See 4 more Smart Citations

Comparator-based switched-capacitor pipelined analog-to-digital converter with comparator preset, and comparator delay compensation

Wulff

Ytterdal

2010

Analog Integr Circ Sig Process

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We present a differential comparator-based switched-capacitor (CBSC) pipelined analog-to-digital converter (ADC) with comparator preset, and comparator delay compensation. Compensating for the comparator delay by digitally adjusting the comparator threshold improves the ADC resolution from 2.5-bit to 7.05-bit. The ADC is manufactured in a 90 nm CMOS technology, with a core area of 0.85 mm 9 0.35 mm, a 1.2 V supply for the core and 1.8 V for the input switches. It has an effective number of bits (ENOB) of 7.05-bit, and a power dissipation of 8.5 mW at 60 MS/s.

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Section: Sampling Of Stage Outputmentioning

confidence: 99%

Section: Comparator-based Switched-capacitor Circuitsmentioning

confidence: 99%

Section: Sampling Of Stage Outputmentioning

confidence: 99%

Section: Comparator Delay Compensationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

Comparator-based switched-capacitor pipelined analog-to-digital converter with comparator preset, and comparator delay compensation

Wulff

Ytterdal

2010

Analog Integr Circ Sig Process

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Nonlinear current source charge scheme for comparator based switched capacitor integrator

Valianpour¹,

Chaharmahali

Biabanifard³

2019

Int J Numerical Modelling

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The continuous development of complementary metal-oxide-semiconductor (CMOS) technology makes it difficult to design high speed and low power amplifiers. One of the appropriate alternatives is comparator-based circuits.In this paper, a modified structure for comparator-based switched-capacitor integrator is presented. This structure increases the clock frequency considerably by using a nonlinear current source. The proposed integrator involves replacing the two linear current sources in conventional comparator-based switched-capacitor integrator with just one nonlinear current source. Also, the new logic part is presented, which reduces the circuit size and power dissipation consequently. The suggested circuit reduces integration dependency to the logic part while decreases charge transfer phases to just a single phase. According to the proposed structure, a first order comparator-based switched-capacitor integrator is designed in 0.18 μm complementary metaloxide-semiconductor technology with a 100 MHz as the clock frequency.

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Characterization and Specification

Pelgrom

2012

Analog-to-Digital Conversion

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Comparator-based switched-capacitor circuits for scaled CMOS technologies

Cited by 127 publications

References 3 publications

Comparator-based switched-capacitor pipelined analog-to-digital converter with comparator preset, and comparator delay compensation

Comparator-based switched-capacitor pipelined analog-to-digital converter with comparator preset, and comparator delay compensation

Nonlinear current source charge scheme for comparator based switched capacitor integrator

Characterization and Specification

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