Comparative Validation of SRAM Cells Based on Decoupled Read Technique using 45nm CMOS

Bhavani, Saranga; Gupta, Lipika; Sachdeva, Ashish; Sharma, Tripti

doi:10.1109/csnt57126.2023.10134659

Cited by 2 publications

References 33 publications

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Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technology

Praveen,

Singh

2024

Circuit Theory & Apps

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The excessive power usage in modern digital equipment is triggered by memory arrays, mainly including Static Random‐Access Memory (SRAM) chips. Many scientists are working to create an SRAM cell that is fast, highly stable, and uses little power. However, the traditional SRAM cells have instability and read/write failure at scaled technology nodes. This study proposes a Differential Power Schmitt‐Trigger Logic 9 Tcompute SRAM (DPSTL‐9 TCSRAM) cell design with high read‐and‐write stability and low energy consumption. In SRAM cells, the sensing amplifier (SA), pre‐charge circuit, row decoder, and column decoder are the primary operational elements. Through the use of a single‐bitline (SBL) configuration and a one‐sided Schmitt‐trigger (ST) inverter (STI), the proposed deisgn cell achieves an outstanding read stability performance. In this work, the differential Power Generation (DPG) technique is employed to improve the architecture's writing capacity. The standard AND gates are combined with Schmitt‐trigger logic AND gates to improve noise tolerance while consuming less power and taking up less space. Instead of using a power‐gating mechanism, this research focuses on modifying a power delay product (PDP) circuit to increase the cell's read‐and‐write operation efficiency. The modified decoupled SA plays a major role in the access time and provides significant benefits in terms of read latency. Tanner EDA Tool platform version 16.0 can be used to execute the specified design. The performance metrics of stability, area, latency, and power analysis are examined, and also, the Monte Carlo simulation and reliability simulation are conducetd to show the efficacy of the proposed design.

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Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technology

Praveen,

Singh

2024

Circuit Theory & Apps

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Design a Gated PMOS Spillage Reduction Approach for CMOS SRAM Cell in 90nm Technology Node

Mittal

2023

2023 14th International Conference on Computing Communication and Networking Technologies (ICCCNT)

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Comparative Validation of SRAM Cells Based on Decoupled Read Technique using 45nm CMOS

Cited by 2 publications

References 33 publications

Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technology

Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technology

Design a Gated PMOS Spillage Reduction Approach for CMOS SRAM Cell in 90nm Technology Node

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