Low power and noise‐immune 9 T compute SRAM cell design based on differential power generator and Schmitt‐trigger logics with14 nm FinFET technology
Pushkar Praveen,
Rakesh Kumar Singh
Abstract:The excessive power usage in modern digital equipment is triggered by memory arrays, mainly including Static Random‐Access Memory (SRAM) chips. Many scientists are working to create an SRAM cell that is fast, highly stable, and uses little power. However, the traditional SRAM cells have instability and read/write failure at scaled technology nodes. This study proposes a Differential Power Schmitt‐Trigger Logic 9 Tcompute SRAM (DPSTL‐9 TCSRAM) cell design with high read‐and‐write stability and low energy consum… Show more
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