Comparative study of CA with phase shifters and GLFSRs

Chidambaram, S.; Kagaris, D.; Pradhan, Dhiraj K.

doi:10.1109/test.2005.1584058

Cited by 10 publications

(6 citation statements)

References 9 publications

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“…An alternative approach is to use a cellular automata-based generator [4,5]. The use of Galois LFSRs (GLFSRs) as test pattern generators for BIST schemes employing multiple scan chains is investigated in [6,7]. The effectiveness of such techniques can be enhanced by using some information about the circuit under test and tailoring the generator hardware to achieve higher coverage faster [8].…”

Section: Introductionmentioning

confidence: 99%

Antirandom Testing: A Distance‐Based Approach

Jandhyala

Malaiya

et al. 2008

VLSI Design

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Random testing requires each test to be selected randomly regardless of the tests previously applied. This paper introduces the concept of antirandom testing where each test applied is chosen such that its total distance from all previous tests is maximum. This spans the test vector space to the maximum extent possible for a given number of vectors. An algorithm for generating antirandom tests is presented. Compared with traditional pseudorandom testing, antirandom testing is found to be very effective when a high-fault coverage needs to be achieved with a limited number of test vectors. The superiority of the new approach is even more significant for testing bridging faults.

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Section: Introductionmentioning

confidence: 99%

Antirandom Testing: A Distance‐Based Approach

Jandhyala

Malaiya

et al. 2008

VLSI Design

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“…In addition, the information only about the configuration of the LHCA 90/150 register is insufficient for an unambiguous indication of the register outputs affected by the mentioned problem. The foregoing observation is also confirmed in [14], even with an additional conclusion that the problem with insufficient separation between a portion of output channels relates to as much as about 75% of structures developed for LHCA 90/150 registers associated with primitive polynomials. Similarly, two-dimensional Tree-structured Linear Cellular Automata (TLCA) also exhibited very low values of the phase shift between a portion of bit sequences appearing at outputs of the register [46].…”

Section: Examplementioning

confidence: 58%

“…The phase shift between binary bitstreams supplied to individual scan paths is also referred to as the separation factor between data channels or between scan paths' content [3] (pp. 184-188), [13,14,34,37,39].…”

Section: Examplementioning

confidence: 99%

“…Please note that in cases when the presumed offset Θ is known, Table 2 makes it possible to find out 𝑛 and 𝑡 parameters of the appropriate DT-LFSR register to enable designing of a TPG that is able to supply test sequences to any number of scan paths, or at least as many as practicable. 15 6.21×10 14 3.11×10 14 1.55×10 14 7.76×10 13 3.88×10 13 12 59 60 1.53×10 14 7.63×10 13 3.82×10 13 1.91×10 13 9.54×10 12 4.77×10 12 13 59 68 3.91×10 16 1.95×10 16 9.77×10 15 4.89×10 15 2.44×10 15 1.22×10 15 14 62 63 1.16×10 15 5.81×10 14 2.91×10 14 1.45×10 14 7.26×10 13 3.63×10 13 15 62 71 2.98×10 17 1.49×10 17 7.44×10 16 3.72×10 16 1.86×10 16 9.30×10 15 16 65 71 2.84×10 17 1.42×10 17 7.09×10 16 3.55×10 16 1.77×10 16 8.87×10 15 17 65 81 2.91×10 20 1.45×10 20 7.27×10 19 3.63×10 19 1.82×10 19 9.08×10 18 18 70 79 6.75×10 19 3.37×10 19 1.69×10 19 78 95 3.97×10 24 1.98×10 24 9.92×10 23 4.96×10 23 2.48×10 23 1.24×10 23 22 84 95 3.68×...…”

Section: Pseudo-random Pattern Generator Dt-lfsr-tpg For Lbist Circuits With the Stumps Architecturementioning

confidence: 99%

“…72-75), [10][11][12][13]. Some specific solutions may also comprise other types of linear registers such as PRPG modules, for instance Galois Linear Feedback Shift Register (GLFSR) [14][15][16]. Responses to test vectors gathered from outputs of a CUT are loaded in the parallel mode into scan paths, and then scan paths are switched to the serial mode and information from all scan paths is supplied to inputs of the MISR module where information is subject to compaction (lossy compression).…”

Section: Introductionmentioning

confidence: 99%

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A New, Fast Pseudo-Random Pattern Generator for Advanced Logic Built-In Self-Test Structures

Garbolino

2021

Applied Sciences

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Digital cores that are currently incorporated into advanced Systems on Chip (SoC) frequently include Logic Built-In Self-Test (LBIST) modules with the Self-Test Using MISR/Parallel Shift Register Sequence Generator (STUMPS) architecture. Such a solution always comprises a Pseudo-Random Pattern Generator (PRPG), usually designed as a Linear Feedback Shift Register (LFSR) with a phase shifter attached to the register and arranged as a network of XOR gates. This study discloses an original and innovative structure of such a PRPG unit referred to as the DT-LFSR-TPG module that needs no phase shifter. The module is designed as a set of identical linear registers of the DT-LFSR type with the same primitive polynomial. Each register has a form of a ring made up exclusively of D and T flip-flops. This study is focused on the investigation of those parameters of DT-LFSR registers that are essential to use these registers as components of PRPG modules. The investigated parameters include phase shifts and the correlation between sequences of bits appearing at outputs of T flip-flops, implementation cost, and the maximum frequency of the register operation. It is demonstrated that PRPG modules of the DT‑LFSR‑TPG type enable much higher phase shifts and substantially higher operation frequencies as compared to competitive solutions. Such modules can also drive significantly more scan paths than other PRPGs described in reference studies and based on phase shifters. However, the cost of the foregoing advantages of DT-LFSR-TPG modules is the larger hardware overhead associated with the implementation of the solution proposed.

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