Calculation of LFSR Seed and Polynomial Pair for BIST Applications

Jutman, Artur; Tsertov, Anton; Ubar, Raimund

doi:10.1109/ddecs.2008.4538801

Cited by 4 publications

(3 citation statements)

References 10 publications

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“…For Design D, as an example, an area overhead of 0.49% can reduce pattern count and test time by 71% at I SFF−thr = 20. In the table, Columns 5,8,11,and 14 show the number of gates inserted due to DT cells. Note that the number of gates inserted is greater than DT cells because each DT cell is made up few gates.…”

Section: Results and Analysismentioning

confidence: 99%

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LBIST pattern reduction by learning ATPG test cube properties

Contreras

Zhao

Ahmed

et al. 2015

Sixteenth International Symposium on Quality Electronic Design

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Logic built-in self-test (LBIST) is commonly used for testing integrated circuits (ICs) in production and in the field. Due to the random nature of LBIST patterns, activation of random-patternresistant faults requires the application of numerous patterns, thus increasing test time in the field. In this work, we introduce a novel method to reduce LBIST pattern count and LBIST test time. The presented technique collects deterministic pattern properties to guide our deterministic test (DT) cell selection and insertion algorithm. The inserted DT cells enhance LBIST patterns quality and reduce pattern count by introducing deterministic-like properties. Experimental results on academic benchmarks and industry designs demonstrate 30% to 70% reduction in pattern count.978-1-4799-7581-5/15/$31.00

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Section: Results and Analysismentioning

confidence: 99%

“…As an example, [4] was successful at reducing test data volume through the use of embedded deterministic test which can generate deterministic patter ns with var ious input s equences . Reseeding: Such methods use various reseeding algorithms and added hardware designed to generate more effective random patterns [9]- [11].…”

Section: Introductionmentioning

confidence: 99%

LBIST pattern reduction by learning ATPG test cube properties

Contreras

Zhao

Ahmed

et al. 2015

Sixteenth International Symposium on Quality Electronic Design

View full text Add to dashboard Cite

show abstract

“…However, the on-chip ROM may induce high area overhead and the ROM itself needs extra test techniques (such as memory BIST). To reduce the required ROM space, some reseeding techniques [5][6] have been proposed to compress the required test data into some small-size seeds, which can then be decompressed by an LFSR or similar logic during test application time.…”

Section: Introductionmentioning

confidence: 99%

A Complete Logic BIST Technology with No Storage Requirement

Lien

Lee

2010

2010 19th IEEE Asian Test Symposium

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Mixed-mode BIST enhances test efficiency of digital circuits by combining the advantages of both pseudorandom and deterministic patterns. In order to apply the deterministic patterns, most traditional methods need to store some test data in external testers or on-chip memory. In this paper we present a novel mixed-mode BIST technique by which all deterministic patterns can be generated on chip in real time and thus requiring no storage device. By appropriately connecting some internal nets of the circuit under test to the inputs of the circuit, together with a set of pseudo-random patterns, this BIST scheme can reach full fault coverage in a very short time. Experimental results show that all irredundant stuck-at faults in each of the ISCAS85 benchmarks can be detected in less than 1000 test cycles with no storage space required.

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A Novel Seed Selection Algorithm for Test Time Reduction in BIST

Chakraborty

Chowdhury

2009

2009 Asian Test Symposium

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Calculation of LFSR Seed and Polynomial Pair for BIST Applications

Cited by 4 publications

References 10 publications

LBIST pattern reduction by learning ATPG test cube properties

LBIST pattern reduction by learning ATPG test cube properties

A Complete Logic BIST Technology with No Storage Requirement

A Novel Seed Selection Algorithm for Test Time Reduction in BIST

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