Comparative Study Of 3D Package Configurations In Power Delivery And Thermal Perspective

Lee, Heeseok; Im, Yunhyeok; Shin, Youngmin

doi:10.23919/iwlpc.2018.8573271

Cited by 8 publications

(3 citation statements)

References 9 publications

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“…Prior research has modelled and analyzed different types of PDN structures for 3D ICs as well as 3D-stacked DRAMs. In [1], different 3D-stacked DRAM package configurations were analyzed and compared from a thermal and power delivery perspectives. In [2], various PDN models were analyzed for various 3D-stacked DRAM architectures (including HMC) that involved replacing TSVs with redistribution layers.…”

Section: Related Workmentioning

confidence: 99%

“…Although the 3D-stacked DRAM architectures have shown significant performance improvements over the conventional 2D DRAM architectures, efforts for further improving their performance and realizing their true potential are still underway. These efforts include restructuring of 3D data organization [11][13] [14][18]- [20], mitigating thermal effects [1][21]- [23], and enhancing I/O interfaces [24]- [26].…”

Section: Introductionmentioning

confidence: 99%

“…This becomes the main cause that limits the performance benefits of the inherent access parallelism of 3D-stacked DRAMs, especially because the constraint on parallelism put forth by the tFAW (four bank-activates window) timing parameter is becoming irrelevant in modern DRAMs due to the diminishing dependence of the PDN on the current delivery capacity of on-chip charge pumps [5]. To this end, several prior works have focused on characterizing and mitigating the adverse effects of PDN IR-drop noise on the performance of 3D-stacked DRAM architectures [1]- [3] [5]. These works also point to the critical importance of understanding various other types of PDN-related adverse effects that can potentially harm the performance of 3D-stacked DRAMs.…”

Section: Introductionmentioning

confidence: 99%

See 2 more Smart Citations

Characterization and Mitigation of Electromigration Effects in TSV-Based Power Delivery Network Enabled 3D-Stacked DRAMs

Bose

Thakkar

2021

Proceedings of the 2021 on Great Lakes Symposium on VLSI

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With 3D-stacked DRAM architectures becoming more prevalent, it has become important to find ways to characterize and mitigate the adverse effects that can hinder their inherent access parallelism and throughput. One example of such adversities is the electromigration (EM) effects in the through-silicon vias (TSVs) of the power delivery network (PDN) of 3D-stacked DRAM architectures. Several prior works have addressed the effects of EM in TSVs of 3D integrated circuits. However, no prior work has addressed the effects of EM in the PDN TSVs on the performance and lifetime of 3D-stacked DRAMs. In this paper, we characterize the effects of EM in PDN TSVs on a Hybrid Memory Cube (HMC) architecture employing the conventional PDN design with clustered layout of power and ground TSVs. We then present a new PDN design with a distributed layout of power and ground TSVs and show that it can mitigate the adverse effects of EM on the HMC architecture performance without requiring additional power and ground pins. Our benchmark-driven simulation-based analysis shows that compared to the clustered PDN layout, our proposed distributed PDN layout improves the EM-affected lifetime of the HMC architecture by up to 10 years. During this useful lifetime, the HMC architecture yields up to 1.51× less energy-delay product (EDP).

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Section: Related Workmentioning

confidence: 99%