Comparative physical and electrical metrology of ultrathin oxides in the 6 to 1.5 nm regime

Ahmed, K.; Ibok, E.; Bains, Gurjeet S.; Chi, Dongzhi; Ogle, B.; Wortman, J. J.; Hauser, John R.

doi:10.1109/16.848276

Cited by 32 publications

(11 citation statements)

References 21 publications

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“…We then estimate A ∼ 18 Å 2 . Using this parameter and the vapor-deposited SiO 2 dielectric constant ε = 4 established previously for thin SiO 2 films, we obtain a voltage drop V B ≈ 2 V, which suffices to understand the experimental data. Note that the above results are admittedly (and pragmatically) approximate.…”

Section: Discussionmentioning

confidence: 67%

Nanometer-Scale Dielectric Self-assembly Process for Anode Modification in Organic Light-Emitting Diodes. Consequences for Charge Injection and Enhanced Luminous Efficiency

et al. 2002

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Layer-by-layer, self-limiting chemisorptive siloxane self-assembly using Si3O2Cl8 as the precursor affords thin, conformal, relatively dense, largely pinhole-free dielectric films that can be deposited on oxide surfaces with sub-nanometer control of film thickness (8.3(1) Å/layer). Deposition chemistry, microstructure, and hole injection/work function modification properties of these (SiO2) x -like films on single-crystal Si(111) and polycrystalline indium tin oxide (ITO) substrates have been characterized by synchrotron specular X-ray reflectivity, cyclic voltammetry, X-ray and UV photoelectron spectroscopy, and atomic force microscopy. Chemisorption of these (SiO2) x films onto the ITO anodes of three-layer, vapor-deposited organic electroluminescent devices (ITO/(SiO2) x /TPD/Alq/Al) nearly triples the external quantum and luminous efficiencies. The efficiency enhancement is attributed to hole and electron injection fluence balance caused by modification of the effective voltage profile brought about by the assembly of well-ordered siloxane layers. Interestingly, as a function of increasing (SiO2) x layer thickness, device turn-on voltage first increases (x = 0 → 1), progressively decreases (x = 1 → 2 → 3), and then increases (x = 3 → 4). A theoretical model based upon computation at the ab initio level is proposed in which the self-assembled dielectric layers induce an additional, thickness-dependent “built-in” electric field across the organic transport layers, thereby simultaneously enhancing electron injection from the cathode (increasing luminescence efficiency) and decreasing the efficiency of hole injection (changing the turn-on voltage).

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Section: Discussionmentioning

confidence: 67%

Nanometer-Scale Dielectric Self-assembly Process for Anode Modification in Organic Light-Emitting Diodes. Consequences for Charge Injection and Enhanced Luminous Efficiency

et al. 2002

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“…Mobility characterization for these type-I devices are also compared with devices having significant hole trapping under NBTI stress (type-II devices with higher effective oxide thickness (EOT) and N 2 dose [26][27][28]). Nitrogen concentration (%N) for the oxynitride samples is determined using X-ray Photoelectron Spectroscopy (XPS) [29] and physical thickness (T PHY ) is determined using XPS [29] and optical method [30]. For each sample, we measure the gate capacitance (C G ) at different gate voltage (V G ).…”

Section: Device Details and Experimentsmentioning

confidence: 99%

Mobility degradation due to interface traps in plasma oxynitride PMOS devices

Islam

Maheta

Das

et al. 2008

2008 IEEE International Reliability Physics Symposium

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Mobility degradation due to generation of interface traps (Δμ eff (N IT )) is a well-known phenomenon that has been theoretically interpreted by several mobility models. Based on these analysis, there is a general perception that Δμ eff (N IT ) is relatively insignificant (compared to Δμ eff due to ionized impurity) and as such can be safely ignored for performance and reliability analysis. Here, we investigate the importance of considering Δμ eff (N IT ) for reliability analysis by analyzing a wide variety of plasma oxynitride PMOS devices using both parametric and physical mobility models. We find that contrary to popular belief this correction is fundamentally important for robust and uncorrupted estimates of the key reliability parameters like threshold-voltage shift, lifetime projection, voltage acceleration factor, etc. Therefore, in this paper, we develop a generalized algorithm for estimating Δμ eff (N IT ) for plasma oxynitride PMOS devices and systematically explore its implications for NBTI-specific reliability analysis.

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“…1 However, the metrology for accurately measuring oxide thickness by physical and electric methods has not been fully established for ultrathin oxides with T ox Ͻ10 nm. Recently, high-resolution transmission electron microscopy ͑HRTEM͒ and spectroscopic ellipsometry ͑SE͒ have been used to measure the physical thickness of nm gate oxides, [2][3][4] and the electric analysis methods such as current-voltage (I -V) and capacitance-voltage (C -V) have been modified to include both quantum 5 and polydepletion effects. 6 In this work, medium energy ion scattering ͑MEIS͒, SE, HRTEM, capacitance-voltage, and current-voltage analysis methods were used to determine the physical and electrical thickness of silicon dioxide films grown by wet oxidation.…”

Section: Introductionmentioning

confidence: 99%

Measurement of the physical and electrical thickness of ultrathin gate oxides

Chang¹,

Yang²,

Hwang³

et al. 2002

Journal of Vacuum Science &Amp; Technology B: Microelectronics and Nanometer Structures Processing, Measurement, and Phenomena

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To evaluate the reliability in measurements of the thickness of ultrathin gate oxides in the range of 2–9 nm, various techniques based on different methodologies were used for comparison. The physical thickness was determined with medium energy ion scattering spectroscopy (MEIS), high-resolution transmission electron microscopy (HRTEM), and spectroscopic ellipsometry (SE). The physical thickness was compared with the electrical thickness measured with current–voltage (I–V) and capacitance–voltage (C–V) measurements with quantum effect corrections. The physical thickness of amorphous SiO2 layers in the range of 2–9 nm determined with MEIS and HRTEM is in a good agreement with the corresponding electrical thickness from C–V and I–V measurements within 0.3 nm. For SE, which is the main technique used for in-line monitoring, we observed that it can be used for 2–9 nm ultrathin gate oxides but is more sensitive to the details of the oxide characteristics.

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Comparative physical and electrical metrology of ultrathin oxides in the 6 to 1.5 nm regime

Cited by 32 publications

References 21 publications

Nanometer-Scale Dielectric Self-assembly Process for Anode Modification in Organic Light-Emitting Diodes. Consequences for Charge Injection and Enhanced Luminous Efficiency

Nanometer-Scale Dielectric Self-assembly Process for Anode Modification in Organic Light-Emitting Diodes. Consequences for Charge Injection and Enhanced Luminous Efficiency

Mobility degradation due to interface traps in plasma oxynitride PMOS devices

Measurement of the physical and electrical thickness of ultrathin gate oxides

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