Comparative Analysis of MTJ/CMOS Hybrid Cells Based on TAS and In-Plane STT Magnetic Tunnel Junctions

Jovanovic, Bojan; Brum, Raphael Martins; Torres, Lionel

doi:10.1109/tmag.2014.2347009

Cited by 12 publications

(8 citation statements)

References 33 publications

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“…To make this possible, it is required to insert STT-MRAM at both register level and memory level. A typical flip-flop (FF) based on STT-MRAM is designed to have a dual-storage facility (hybrid) [9]. The CMOS stage of the FF uses crosscoupled inverters (latch) to store one data bit in its electrical (volatile) form.…”

Section: A Instant-on/offmentioning

confidence: 99%

Embedded systems to high performance computing using STT-MRAM

Senni

Delobelle

Coi

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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Abstract-The scaling limits of CMOS have pushed many researchers to explore alternative technologies for beyond CMOS circuits. In addition to the increased device variability and process complexity led by the continuous decreasing size of CMOS transistors, heat dissipation effects limit the density and speed of current systems-on-chip. For beyond CMOS systems, the emerging memory technology STT-MRAM is seen as a promising alternative solution. This paper shows first how STT-MRAM can improve energy efficiency and reliability of future embedded systems. Then, a hybrid design exploration framework is presented to investigate the potential of STT-MRAM for high performance computing.

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Section: A Instant-on/offmentioning

confidence: 99%

Embedded systems to high performance computing using STT-MRAM

Senni

Delobelle

Coi

et al. 2017

Design, Automation &Amp; Test in Europe Conference &Amp; Exhibition (DATE), 2017

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“…Among all of the flip-flops (FFs) of the SecretBlaze (Amber), 1,986 (1,644) FFs contain the state of the processor. A typical FF based on STT-MRAM is designed to have a dual-storage facility (Figure 2a) [16]. The CMOS stage of the FF uses cross-coupled inverters (latch) to store one data bit in its electrical (volatile) form.…”

Section: Non-volatile Computing a Normally-off Computingmentioning

confidence: 99%

“…because of an execution error), only the modified memory locations are restored. An alternative solution to perform a checkpoint at memory level could be the use of a double context non-volatile SRAM cell as proposed in [16]. Considering such a nonvolatile memory based on this cell, it is possible to optimize the silicon area overhead and to greatly simplify the backup of the main memory.…”

Section: B Checkpointing/rollback Mechanismmentioning

confidence: 99%

Normally-Off Computing and Checkpoint/Rollback for Fast, Low-Power, and Reliable Devices

et al. 2017

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Since the advent of complementary metal oxide semiconductors (CMOS), the number of transistor per die never stops increasing to reach today several billion of transistors. As a result, design and fabrication of smart devices able to run at high speed has been possible. However, the power consumption of systems-on-chip has significantly increased due to the high density integration and the high leakage power of current CMOS transistors. As a result, a heat dissipation wall makes difficult further improvement in performance. Having high autonomy for battery-powered devices becomes a real challenge. To deal with these issues, STT-MRAM technology is seen as a promising solution. In addition to its attractive performance features, STT-MRAM can bring non-volatility inside a system to allow full data retention after a complete shutdown while keeping a fast wake-up time. Considering two 32-bit embedded processors, this paper shows how STT-MRAM can improve energy efficiency and reliability of future embedded systems thanks to normally-off computing and checkpointing/rollback techniques. Finally, a detailed analysis is performed to evaluate the cost related to the backup/recovery of the system. Index Terms-Spintronic memory and logic, embedded processor.

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“…This size depends on both the application and the checkpointing period. An alternative solution to perform a checkpoint at memory level is the use of a double context non-volatile SRAM cell as proposed in Jovanovic et al [2015]. Hence, it is possible to optimize the silicon area overhead.…”

Section: Rollbackmentioning

confidence: 99%

“…Within the context of energy-harvesting and IoT applications, Wang et al [2010] and Jovanović et al [2014] proposed a non-volatile FF respectively based on ferroelectric RAM (FeRAM) and OxRAM and validated by simulation the possibility to save/restore the logic state after a power-off of the device. Jovanovic et al [2015], whose results have been used in this work for TAS-MRAM-based FFs, have made an exhaustive performance/energy analysis of a set of hybrid CMOS/MTJ cells that can be used for both data storage and logic devices in SoCs. Chabi et al [2014], Jovanović et al [2014], and Choi et al [2013], whose results have been also used in this article, proposed respectively a hybrid CMOS/STT-MRAM FF, hybrid CMOS/OxRAM FF, and hybrid CMOS/PCRAM FF to allow system power-off in sleep mode.…”

Section: Non-volatile Logic Elementsmentioning

confidence: 99%

Non-Volatile Processor Based on MRAM for Ultra-Low-Power IoT Devices

Senni

Torres

Sassatelli

et al. 2016

J. Emerg. Technol. Comput. Syst.

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Over the past few years, a new era of smart connected devices has emerged in the market to enable the future world of the Internet of Things (IoT). A key requirement for IoT applications is the power consumption to allow very high autonomy in the case of battery-powered systems. Depending on the application, such devices will be most of the time in a low-power mode (sleep mode) and will wake up only when there is a task to accomplish (active mode). Emerging non-volatile memory technologies are seen as a very attractive solution to design ultra-low-power systems. Among these technologies, magnetic random access memory is a promising candidate, as it combines non-volatility, high density, reasonable latency, and low leakage. Integration of non-volatility as a new feature of memories has the great potential to allow full data retention after a complete shutdown with a fast wake-up time. This article explores the benefits of having a non-volatile processor to enable ultra-low-power IoT devices.

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Comparative Analysis of MTJ/CMOS Hybrid Cells Based on TAS and In-Plane STT Magnetic Tunnel Junctions

Cited by 12 publications

References 33 publications

Embedded systems to high performance computing using STT-MRAM

Embedded systems to high performance computing using STT-MRAM

Normally-Off Computing and Checkpoint/Rollback for Fast, Low-Power, and Reliable Devices

Non-Volatile Processor Based on MRAM for Ultra-Low-Power IoT Devices

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