Compact Transistor Modelling for Circuit Design

Graaff, H.C. de; Klaassen, F.M.

doi:10.1007/978-3-7091-9043-2

Cited by 210 publications

(51 citation statements)

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“…In view of the size of A, the emitter series resistance r , can be neglected [5]. Assuming T b << T,, formula (13) reduces to S p / f = S,;/f + r;2SvTl/f = aIB + bI:.…”

Section: Figs 2 and 4 In [21] Present The Input Referred Noise E(nv/and)mentioning

confidence: 99%

“…Kleinpenning [4] suggested that these deviations may be ascribed to resistance fluctuations in the internal parasitic series resistances. It is well known that in submicrometer bipolar transistors the influence of the intemal base and emitter series resistances on the 1 , -VEB and 1 , -VEB characteristics at higher currents becomes important [ 5 ] . Recently, papers on low-frequency noise in bipolar transistors have been published taking the influence of the intemal series resistances into account [61, [71. The purpose of this paper is to present a survey of the state-of-the-art of low-frequency noise in modem transistors, like polysilicon emitter bipolar transistors and heterojunction bipolar transistors.…”

Section: Introductionmentioning

confidence: 99%

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Low-frequency noise in modern bipolar transistors: impact of intrinsic transistor and parasitic series resistances

Kleinpenning

1994

IEEE Trans. Electron Devices

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Abstract-In modern submicrometer transistors, the influence of the internal base and emitter series resistances, on both the I-V characteristics and the LF noise at higher bias currents, becomes important. In this paper expressions are presented for the LF noise in transistors, where the influence of the series resistances has been taken into account. The expressions have been compared with recent experimental results from the literature obtained from modern submicrometer (heterojunction) bipolar transistors. At low forward currents the LF noise in such transistors is determined by spontaneous fluctuations in the base and collector currents. In most transistors at higher forward currents, the parasitic series resistances and their noise become important.

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“…In view of the size of A, the emitter series resistance r , can be neglected [5]. Assuming T b << T,, formula (13) reduces to S p / f = S,;/f + r;2SvTl/f = aIB + bI:.…”

Section: Figs 2 and 4 In [21] Present The Input Referred Noise E(nv/and)mentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Low-frequency noise in modern bipolar transistors: impact of intrinsic transistor and parasitic series resistances

Kleinpenning

1994

IEEE Trans. Electron Devices

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“…The effect of channel length modulation (CLM) is modeled using a variant of the Klaasen model [32], [33], suitably modified to avoid numerical difficulties. An alternative linear " " model for CLM can also be used within STAG to facilitate fast parameter extraction at the expense of some accuracy.…”

Section: A Small Geometry Effectsmentioning

confidence: 99%

A physically based compact model of partially depleted SOI MOSFETs for analog circuit simulation

Lee

Tenbroek

Redman-White

et al. 2001

IEEE J. Solid-State Circuits

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Abstract-In this paper, the Southampton Thermal AnaloGue (STAG) compact model for partially depleted (PD) silicon-on-insulator (SOI) MOSFETs is presented. The model uses a single expression to model the channel current, thereby ensuring continuous transition between all operating regions. Furthermore, care has been taken to ensure that this expression is also infinitely differentiable, resulting in smooth and continuous conductances and capacitances as well as higher order derivatives. Floating-body effects, which are particular to PD SOI and which are of concern to analog circuit designers in this technology, are well modeled. Small geometry effects such as channel length modulation (CLM), drain-induced barrier lowering (DIBL), charge sharing, and high field mobility effects have also been included.Self-heating (SH) effects are much more apparent in SOI devices than in equivalent bulk devices. These have been modeled in a consistent manner, and the implementation in SPICE3f5 gives the user an additional thermal node which allows internal device temperature rises to be monitored and also accommodates the modeling of coupled heating between separate devices. The model has been successfully used to simulate a variety of circuits which commonly cause problems with convergence. Due to its inherent robustness, the model can normally achieve convergence without recourse to the setting of initial nodal voltage estimates.

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“…Advanced technology can make people at a reasonable cost of rapid design and manufacture of complex circuits, with the loss of the product cost, increasing proportion of the total cost of testing [1][2].…”

Section: Introductionmentioning

confidence: 99%

Research on the Genetic Algorithm and the Convex Optimization Theory and the Applications on the Large Scale Integrated Circuit Design

Xu¹,

Shi²

2016

Proceedings of the 2016 International Conference on Mechatronics Engineering and Information Technology

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Abstract. In this literature article, we conduct research on genetic algorithm and convex optimization theory and the applications on the large scale integrated circuit design. Integrated circuit test system's main function is to test the microprocessor, semiconductor memory circuit and a variety of dedicated circuit and the high performance test system can complete function test and the dc parameters test, ac parameters. Basic test system structure consists of computer subsystem and the testing and measuring subsystem. Under this basis, we propose the novel perspective of the large scale integrated circuit design pattern that will promote the VSLI industry in China.

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Compact Transistor Modelling for Circuit Design

Cited by 210 publications

References 0 publications

Low-frequency noise in modern bipolar transistors: impact of intrinsic transistor and parasitic series resistances

Low-frequency noise in modern bipolar transistors: impact of intrinsic transistor and parasitic series resistances

A physically based compact model of partially depleted SOI MOSFETs for analog circuit simulation

Research on the Genetic Algorithm and the Convex Optimization Theory and the Applications on the Large Scale Integrated Circuit Design

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