Compact test generation for bridging faults under I/sub DDQ/ testing

Fault models and test generation for IDDQ testing

“…For example, all the detectable ITRA-SHs in a 2-input NAND gate are detected by t e s t v ectors that set (0, 1), (1, 0) and (1, 1) at the two inputs. In previous literature, complete fault coverage is obtained for every ISCAS'85 benchmark combinational circuits [29].…”

“…It is found that random testing is ecient for testing TBFs [17,28,29]. But to obtain complete fault coverage, [3] TBF two line single BF all Dalpasso et al [10] TBF TBF random sample…”

“…In previous literature, 100% fault eciency is obtained for TBFs in every ISCAS'85 benchmark combinational circuit [29]. For sequential circuits, 100% fault eciency is dicult to obtain.…”

“…Reverse order simulation is a simulation technique with applying test vectors in the reverse order, i.e. the last generated test vector is applied rst [19,29]. This may m a k e earlier generated test vectors unnecessary.…”

“…The paper includes following ve techniques; removal of inert subsequences, replacement of inert subsequences, removal with partial substitution, conditional removal of fault-detecting subsequences, conditional removal of inert subsequences. The techniques [20] SAF seq TPG for SAF Chen et al [9] TBF seq TPG for SAF, genetic algorithm Dalpasso et al [10] TBF comb SPICE, BDD Isern & Figueras [17] INTRA-SH, TBF comb TPG for SAF Reddy et al [29] INTRA-SH, TBF comb random tests, TPG for SAF Mahlstedt et al [23] INTRA-SH, TBF comb random tests, deterministic TPG Higami et al [13] INTRA Since measurement of IDDQ is a time-consuming process, reduction of IDDQ measurement v ectors is more effective for reducing the total testing time. Therefore a method to select a small number of IDDQ measurement vectors has been proposed in [5,6,8,14,16,20,26].…”