2020
DOI: 10.1016/j.cryogenics.2020.103069
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Compact Si JFET model for cryogenic temperature

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Cited by 3 publications
(1 citation statement)
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“…As quantum algorithms grow in complexity, leveraging well-established CMOS technology presents an avenue to streamline interconnections, ensuring both the compactness and scalability of quantum processors [18,19]. Despite successful experimental demonstrations of electronic devices functioning at cryogenic temperatures [20,21], the modeling and simulation of these devices at 4 K or lower temperatures remain an ongoing developmental pursuit [22][23][24][25][26][27][28][29][30][31]. Lowering the ambient temperature notably enhances device performance, characterized by reduced thermal noise, an increased I ON /I OFF ratio, and a sharper subthreshold swing.…”
Section: Introductionmentioning
confidence: 99%
“…As quantum algorithms grow in complexity, leveraging well-established CMOS technology presents an avenue to streamline interconnections, ensuring both the compactness and scalability of quantum processors [18,19]. Despite successful experimental demonstrations of electronic devices functioning at cryogenic temperatures [20,21], the modeling and simulation of these devices at 4 K or lower temperatures remain an ongoing developmental pursuit [22][23][24][25][26][27][28][29][30][31]. Lowering the ambient temperature notably enhances device performance, characterized by reduced thermal noise, an increased I ON /I OFF ratio, and a sharper subthreshold swing.…”
Section: Introductionmentioning
confidence: 99%