Compact reliability model for degradation of advanced p-MOSFETs due to NBTI and hot-carrier effects in the circuit simulation

Ma, Chenyue; Mattausch, Hans Jürgen; Miyake, M.; Iizuka, T.; Miura-Mattausch, Mitiko; Matsuzawa, K.; Yamaguchi, S.; Hoshida, T.; Imade, M.; Koh, Risho; Arakawa, Takahiko; He, Jin‐Sheng

doi:10.1109/irps.2013.6531943

Cited by 22 publications

(6 citation statements)

References 22 publications

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“…In practice, the MOSFET is exposed to several stress conditions such as hot carrier (HC) and off-state stress, in addition to NBTI stress. 36,37) During HC and off-state stress, both a vertical stress electric field and a lateral stress electric field are applied. 36,37) The lateral stress electric field affects the defect density near the drain varies based on L gate , so using only the method proposed in the paper, length dependence of ΔV th cannot be easily predicted based on HC and off-state stress.…”

Section: Stress Time [S]mentioning

confidence: 99%

“…36,37) During HC and off-state stress, both a vertical stress electric field and a lateral stress electric field are applied. 36,37) The lateral stress electric field affects the defect density near the drain varies based on L gate , so using only the method proposed in the paper, length dependence of ΔV th cannot be easily predicted based on HC and off-state stress. Thus, the proposed method (or other methods to be proposed) should consider the components related to the lateral stress electric field.…”

Section: Stress Time [S]mentioning

confidence: 99%

See 1 more Smart Citation

Method to predict length dependency of negative bias temperature instability degradation in p-MOSFETs

Seo

Kim

Son

et al. 2016

Jpn. J. Appl. Phys.

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We propose a method to predict the length dependency of the magnitude of degradation caused by negative bias temperature instability (NBTI) stress applied to a p-MOSFET. Threshold voltage degradation ΔV th varied according to the drain bias V d, during the measurement of drain current I d. The depletion length L dep into the channel was calculated based on a particular V d value and the channel doping concentration. L dep was used to extract the channel edge region length L edge, then the center channel region length L cen was obtained by subtracting L edge from the gate length L gate. We proposed an equation that uses L dep, L cen, L edge and degree of ΔV th variation to calculate ΔV th according to L gate while the p-MOSFET is under NBTI stress. Equation estimates of ΔV th at different L gate were similar to measurements.

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Section: Stress Time [S]mentioning

confidence: 99%

Section: Stress Time [S]mentioning

confidence: 99%

Method to predict length dependency of negative bias temperature instability degradation in p-MOSFETs

Seo

Kim

Son

et al. 2016

Jpn. J. Appl. Phys.

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“…There are series of papers that follow changes of interface traps over time. [39][40][41][42][43][44] These papers focused on negative bias temperature instability and hot carrier degradation, and follow trap dynamics in stress time scales. There are another series of papers concerning the compact modeling which successfully describe measured dynamical change of terminal currents affected by traps.…”

Section: Introductionmentioning

confidence: 99%

A time-dependent Verilog-A compact model for MOS capacitors with interface traps

Fukuda

Asai

Hattori

et al. 2019

Jpn. J. Appl. Phys.

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A modeling method to analyze transient behaviors of MOS capacitors including interface traps by circuit simulation is proposed. Through applications to GaN MOS capacitors, plateau, frequency dispersion, and hysteresis are obtained as typical trap influences on C–V characteristics. Examples of more complicated cases are demonstrated, including the influence of the energy distribution of the trap, cases with multiple peaks in the trap energy distribution, cases where resistors are connected in series as a circuit. Through these examples, it is expected that this modeling method using circuit simulation will be useful for modeling experimental results of trap-affected MOS capacitors.

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“…The objective of including a reliability improving circuit (RIC) in a CMOS architecture is to reduce variation in the system's figures of merit (FOM). Recent literature has addressed this issue for various radio frequency (RF), digital and digital-to-analog-conversion (DAC) circuits [5,[16][17][18][19][20][21][22][23][24][25][26][27][28][29]. For example, a reliability-sensitive power amplifier is presented in [5] which can be integrated with a wireless fidelity receiver to mitigate discharge/aging issues.…”

Section: Introductionmentioning

confidence: 99%

“…The dependence of hot carrier reliability (HCR) on contact spacing (source/drain) and its subsequent effect on device behaviour in a radiation environment have been discussed in [16]. A compact model for transistor degradation because of channel hot carriers and thermal instability is proposed in [17]. The formulation of a scalable technique has been demonstrated in [18] for analysis of large circuit delay degradations (because of HCR).…”

Section: Introductionmentioning

confidence: 99%

Common‐rail powered reliability improving technique for single‐supply complementary metal oxide semiconductor amplifiers

Roy¹,

Rashid²

2015

IET Circuits, Devices & Systems

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This paper presents a low-power technique to improve reliability of complementary metal oxide semiconductor (CMOS) amplifiers using a shared bias network for input gate and substrate of transistors. The circuit [named reliability improving circuit (RIC)] significantly reduces discrepancy in amplifier gain (S 21 , voltage gain), noise figure (NF/NF min) and output reflection-loss (ORL) parameters resulting from variation in threshold voltage, feature-width, device speed and supply rail. It performs well on both typical-(1.2 V) and low-voltage (0.7 V) platforms of a 90 nm CMOS technology and is able to maintain its consistency within a wide frequency coverage (10-30 GHz) for three different architectures (cascode, low-voltage cascode and common-source). This allows the RIC incorporated front-end to satisfy a broad range of gain, isolation, linearity and NF requirements. The scheme's biasing arrangement is powered from amplifier rails which permit the overall circuit to be driven from a single main supply. Analysis and simulation results demonstrate the technique improving consistency of figures of merit considerably against different aspects of process/system variation without significant degradation of radio frequency performance.

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Compact reliability model for degradation of advanced p-MOSFETs due to NBTI and hot-carrier effects in the circuit simulation

Cited by 22 publications

References 22 publications

Method to predict length dependency of negative bias temperature instability degradation in p-MOSFETs

Method to predict length dependency of negative bias temperature instability degradation in p-MOSFETs

A time-dependent Verilog-A compact model for MOS capacitors with interface traps

Common‐rail powered reliability improving technique for single‐supply complementary metal oxide semiconductor amplifiers

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