A time-dependent Verilog-A compact model for MOS capacitors with interface traps

Abstract

A modeling method to analyze transient behaviors of MOS capacitors including interface traps by circuit simulation is proposed. Through applications to GaN MOS capacitors, plateau, frequency dispersion, and hysteresis are obtained as typical trap influences on C–V characteristics. Examples of more complicated cases are demonstrated, including the influence of the energy distribution of the trap, cases with multiple peaks in the trap energy distribution, cases where resistors are connected in series as a circuit. Through these examples, it is expected that this modeling method using circuit simulation will be useful for modeling experimental results of trap-affected MOS capacitors.