Compact modeling of the high temperature effect on the single event transient current generated by heavy ions in SOI 6T-SRAM

Boufouss, El Hafed; Pulido, José Joaquin Alvarado; Flandre, Denis

doi:10.4071/hitec-eboufouss-ta25

Cited by 7 publications

(3 citation statements)

References 14 publications

(19 reference statements)

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“…A new design of the voltage reference ( Figure 3 ) was developed with a cascoded current source, to reduce the V REF variations due to the process corners, supply voltage variation and mainly the radiation effects caused by single ionized particles [ 10 ]. As it is based on the same principle as the previous design [ 3 ], the voltage reference expression V REF remains unchanged ( Equation (9) ).…”

Section: Circuit Realizationmentioning

confidence: 99%

“…To take into account the variations due to radiation effects, additional constraints were considered as follow: The designed circuit was checked with custom model parameters of transistors including TID effects on transistors [ 11 ] (up to 30% mobilities degradation and negative voltage threshold shifts of 100 mV). Using transistors with a body contact to limit the effect of the parasitic bipolar possibly created by radiation [ 10 ]. Choosing relatively long transistor to assure lower leakage current and lower threshold voltages shift, which may appear as a result of TID and high-temperature effects [ 2 , 12 , 13 ].…”

Section: Circuit Realizationmentioning

confidence: 99%

“…Using transistors with a body contact to limit the effect of the parasitic bipolar possibly created by radiation [ 10 ].…”

Section: Circuit Realizationmentioning

confidence: 99%

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Ultra-Low Power High Temperature and Radiation Hard Complementary Metal-Oxide-Semiconductor (CMOS) Silicon-on-Insulator (SOI) Voltage Reference

Boufouss

Francis

Kilchytska

et al. 2013

Sensors

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This paper presents an ultra-low power CMOS voltage reference circuit which is robust under biomedical extreme conditions, such as high temperature and high total ionized dose (TID) radiation. To achieve such performances, the voltage reference is designed in a suitable 130 nm Silicon-on-Insulator (SOI) industrial technology and is optimized to work in the subthreshold regime of the transistors. The design simulations have been performed over the temperature range of −40–200 °C and for different process corners. Robustness to radiation was simulated using custom model parameters including TID effects, such as mobilities and threshold voltages degradation. The proposed circuit has been tested up to high total radiation dose, i.e., 1 Mrad (Si) performed at three different temperatures (room temperature, 100 °C and 200 °C). The maximum drift of the reference voltage VREF depends on the considered temperature and on radiation dose; however, it remains lower than 10% of the mean value of 1.5 V. The typical power dissipation at 2.5 V supply voltage is about 20 μW at room temperature and only 75 μW at a high temperature of 200 °C. To understand the effects caused by the combination of high total ionizing dose and temperature on such voltage reference, the threshold voltages of the used SOI MOSFETs were extracted under different conditions. The evolution of VREF and power consumption with temperature and radiation dose can then be explained in terms of the different balance between fixed oxide charge and interface states build-up. The total occupied area including pad-ring is less than 0.09 mm2.

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Section: Circuit Realizationmentioning

confidence: 99%