Compact Modeling of SOI MOSFETs With Ultrathin Silicon and BOX Layers

Miura-Mattausch, Mitiko; Feldmann, U.; Fukunaga, Yutaka; Miyake, M.; Kikuchihara, Hideyuki; Ueno, Fumiya; Mattausch, Hans Jürgen; Nakagawa, Tadashi; Sugii, Nobuyuki

doi:10.1109/ted.2013.2286206

Cited by 15 publications

(8 citation statements)

References 28 publications

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“…Qdep describes the depletion charge within the channel. The Poisson equation is solved iteratively together with the boundary conditions at the different material junctions [28,30]. Figure 1b reveals, that HiSIM_MG can realize a good fit to the 2D device simulation results for any bias conditions.…”

Section: Mg-mosfet Features and Their Modelingmentioning

confidence: 94%

Optimization of Low-Voltage-Operating Conditions for MG-MOSFETs

Ghosh

Miura-Mattausch

Iizuka

et al. 2022

IEEE J. Electron Devices Soc.

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Adaptive threshold-voltage controlling of thin-film multi-gate (MG) MOSFETs, using independent back-gate biasing, is applied for realizing latency and power optimization. The controlling-method validity for low-voltage operation is analyzed with the compact model HiSIM-MG, considering all internally induced charges specific for MG controlling. Current-drivability degradations, due to back-gate-charge contribution under positively-biased back-gate voltage and existence of an optimized operating condition, are confirmed. The optimized operating condition is shown to keep the back-gate charge under the weak inversion with a corresponding relatively small back-gate charge. It is also demonstrated, that an input-voltage optimization accompanies the back-gate-voltage optimization, sustaining the optimized low power loss with low input voltage. Circuitperformance improvement of 27% by about 30% reduction of substrate thickness, while keeping switching-power loss small, is also verified.

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Section: Mg-mosfet Features and Their Modelingmentioning

confidence: 94%

Optimization of Low-Voltage-Operating Conditions for MG-MOSFETs

Ghosh

Miura-Mattausch

Iizuka

et al. 2022

IEEE J. Electron Devices Soc.

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“…The potential distribution within the SOTB-MOSFET is a function of applied biases V gs and V bg as well as of the device parameters. To calculate the distribution accurately, the Poisson equation is solved iteratively together with boundary conditions for four potential values [2] (1) where Q i is the mobile charge, is the mobility, and E x is the electric field along the channel. The carrier mobility is determined by the field applied.…”

Section: Modeling Of the Sotb-mosfetmentioning

confidence: 99%

Mobility model for advanced SOI-MOSFETs including back-gate contribution

Zenitani¹,

Kikuchihara²,

Feldmann³

et al. 2015

Jpn. J. Appl. Phys.

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This paper reports a newly developed compact mobility model for very thin SOI and BOX layer MOSFETs. It is demonstrated that the universality of the low-field mobility is still preserved. However, the effective electric field is not only determined by the field induced at surface but modified by the potential distribution across the SOI layer. Measured I-V characteristics are well reproduced under a wide variety of bias conditions.

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“…Such a coupling effect increases the calculation complexity. In the meantime, some models [12][13][14][15] of multiple-gate SOI MOSFETs have been proposed, and some models of FD SG SOI MOSFETs [16][17][18][19][20] incorporating the B-S potential coupling effect are derived. Ravariu et al [16] and Pandey et al [17] developed threshold models for long-and short-channel FD SG SOI MOSFETs, respectively, by numerically solving a complicated equation about the position of the minimum back-channel potential.…”

Section: Introductionmentioning

confidence: 99%

“…Ravariu et al [16] and Pandey et al [17] developed threshold models for long-and short-channel FD SG SOI MOSFETs, respectively, by numerically solving a complicated equation about the position of the minimum back-channel potential. M. Miura-Mattausch et al [18] also proposed an analytical I-V model of FD SG SOI MOSFETs based on a completely potential-based description solving the Poisson's equation iteratively together with additional equations. Here, numerical computation reduced the calculation efficiency.…”

Section: Introductionmentioning

confidence: 99%

A Surface-Potential-Based Analytical I-V Model of Full-Depletion Single-Gate SOI MOSFETs

Huang

et al. 2019

Electronics

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A surface-potential-based analytical I-V model of single-gate (SG) silicon-on-insulator (SOI) MOSFETs in full-depletion (FD) mode is proposed and compared with numerical data and Khandelwal's experimental results. An explicit calculation scheme of surface potential, processing high computation accuracy and efficiency, is demonstrated according to the derivation of the coupling relation between surface potential and back-channel potential. The maximum absolute error decreases into 10 −7 V scale, and computation efficiency is improved substantially compared with numerical iteration. Depending on the surface potential, the drain current is derived in closed-form and validated by Khandelwal's experimental data. High computation accuracy and efficiency suggest that this analytical I-V model displays great promise for SOI device optimizations and circuit simulations.

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Compact Modeling of SOI MOSFETs With Ultrathin Silicon and BOX Layers

Cited by 15 publications

References 28 publications

Optimization of Low-Voltage-Operating Conditions for MG-MOSFETs

Optimization of Low-Voltage-Operating Conditions for MG-MOSFETs

Mobility model for advanced SOI-MOSFETs including back-gate contribution

A Surface-Potential-Based Analytical I-V Model of Full-Depletion Single-Gate SOI MOSFETs

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