Compact low-voltage CMOS current-mode multiplier/divider

Lopez-Martin, A.J.; Bias, Carlos A. De La Cruz; Ramírez-Angulo, J.; Carvajal, R.G.

doi:10.1109/iscas.2010.5537427

Cited by 15 publications

(4 citation statements)

References 9 publications

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“…The experimental power was about 3µW larger than the simulated values due to a larger output capacitance. The results demonstrate the proposed circuit's capability to operate as an NT Type-reducer/defuzzifier for PWM applications with a simpler architecture and with small power consumption, even smaller than the individual power consumption of analog multiplier/divider circuits, such as [39] with 120µW and [40] with 60µW, as shown by the comparison in Table 4.…”

Section: Resultsmentioning

confidence: 74%

A PWM Nie-Tan Type-Reducer Circuit for a Low-Power Interval Type-2 Fuzzy Controller

2021

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A novel Type-Reduction/Defuzzification circuit architecture for an analog interval type-2 fuzzy inference system is proposed. Based on the Nie-Tan type-reduction method, the circuit operates with current-mode inputs, representing the firing intervals of the rules created by the inference engine, and generating a PWM output. It is demonstrated that by selecting an appropriate number of consequents it is possible to create the PWM output directly, without the need for analog multiplier/divider circuits. This feature makes the circuit very simple, aiding in the design process, while the PWM output makes it suitable for controlling DC-DC converters, maximum power point trackers (MPPT) for energy generators, or other switching applications. It is designed to achieve very low power consumption, allowing its use in power restrained environments, such as energy harvesting systems. The circuit was designed using TSMC 0.18µm technology, in CADENCE Virtuoso software, and simulated for different combinations of input values, demonstrating its capabilities. It was also simulated as part of a type-2 fuzzy inference system with two inputs, nine rules, and firing intervals represented by currents within 0 and 10µA. The circuit was prototyped, and the experimental average power consumption was only 53.8µW, validating its low power consumption characteristic.

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Section: Resultsmentioning

confidence: 74%

A PWM Nie-Tan Type-Reducer Circuit for a Low-Power Interval Type-2 Fuzzy Controller

2021

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“…The analysis of the features of solutions [12]- [46], presented in Table I, gives the following conclusions: a) many circuits are not directly suitable for voltage-mode and mixed mode applications because they have insufficiently low impedance of current input terminals [12]- [17], [19]- [24], [27], [28], [32], [35]- [37], [40], [41], [43]- [45], b) voltage input terminals are available in limited number of cases [18], [26], [29]- [31], [33], [34], [38], [39], [42], [46], c) many circuits process only very low-level signals (dynamical limitation) unsuitable for many purposes (especially [13], [17], [23], [38]), in other words only [31] and [46] are acceptable for our purposes but another features are not fulfilled or significant enhancement is required), d) all solutions in Table I have only one single output and, e) the value of output resistance is not known as well as information about its variability when the input levels of the multiplier are changed or DC voltage is connected to selected pair of input terminals in order to operate as operational transconductance amplifier (independence on driving process [47]).…”

Section: Cmos Multipliermentioning

confidence: 99%

Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated Signals

et al. 2021

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This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the of values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain.

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“…However, these amplifiers may increase the power consumption and are commonly implemented using bipolar transistors that require a high supply voltage, generally requiring a negative supply voltage. Another kind of multiplier and divider is based on the unique square characteristic of MOSFET [ 9 , 10 , 11 , 12 ], or the exponential characteristic of the weak inversion region [ 13 , 14 , 15 , 16 ], which can achieve a higher bandwidth, smaller size and lower power consumption. However, due to the limited working area of the transistor, the operation range is narrow.…”

Section: Introductionmentioning

confidence: 99%

An Ultra-Low-Power Analog Multiplier–Divider Compatible with Digital Code for RRAM-Based Computing-in-Memory Macros

Yi-ming

et al. 2023

Micromachines

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This manuscript presents an ultra-low-power analog multiplier–divider compatible with digital code words, which is applicable to the integrated structure of resistive random-access memory (RRAM)-based computing-in-memory (CIM) macros. Current multiplication and division are accomplished by a current-mirror-based structure. Compared with digital dividers to achieve higher precision and operation speed, analog dividers present the advantages of a reduced power consumption and a simple circuit structure in lower precision operations, thus improving the energy efficiency. Designed and fabricated in a 55 nm CMOS process, the proposed work is capable of achieving 8-bit precision for analog current multiplication and division operations. Measurement results show that the signal delay is 1 μs when performing 8-bit operation, with a bandwidth of 1.4 MHz. The power consumption is less than 6.15 μW with a 1.2 V supply voltage. The proposed multiplier–divider can increase the operation capacity by dividing the input current and digital code while reducing the power consumption and complexity required by division, which can be further utilized in real-time operation of edge computing devices.

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Compact low-voltage CMOS current-mode multiplier/divider

Cited by 15 publications

References 9 publications

A PWM Nie-Tan Type-Reducer Circuit for a Low-Power Interval Type-2 Fuzzy Controller

A PWM Nie-Tan Type-Reducer Circuit for a Low-Power Interval Type-2 Fuzzy Controller

Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated Signals

An Ultra-Low-Power Analog Multiplier–Divider Compatible with Digital Code for RRAM-Based Computing-in-Memory Macros

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