Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated Signals

Abstract

This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the of values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain.

Electronically Reconfigurable and Tunable Fractional-Order Filter Using Resonator Concept and Feedforward Path for Low-Frequency Tone Signalization

“…The maximal output DC voltage is available for the largest phase/frequency difference, zero voltage for alignment of the input and reference waves. The overall complexity of both circuits is similar and in [34] the power consumption is lower than in our presented solution (given by the used technology and supply voltage).…”

“…Electronic tuning of the filter brings useful feature because the operation (carrier) frequency can be easily changed (impossible in [29]) and not documented in the rest of works [28], [30]- [32]). The last work [34], regarding to this topic, has very similar features. However, there are significant differences.…”

“…In this paper, the multiplier has a single output (the type of multiplier in this work and in [34] is different and has different internal CMOS topology, i.e. the doubled output voltage is not available here (not necessary heresufficient dynamical ranges of active devices) but the topology is simpler than in [34]). Next, there is difference in the phase response of the "filtering" block in the frequency/phase detector.…”

“…Next, there is difference in the phase response of the "filtering" block in the frequency/phase detector. Work [34] uses a standard firstorder all-pass response (0° → 180°) whereas solution in our actual work employs a special response of fractional-order reconfigurable filter generating inverting all-pass response having phase limits in ±180° (+180° → 180°) with 0° at the target value of the detected frequency (the same as compared). It results in the maximal detected output voltage of the multiplier when the phase difference of signals of the same frequency is zero (or the input frequency of complete phase detector is identical with the setting of the filter).…”

“…It results in the maximal detected output voltage of the multiplier when the phase difference of signals of the same frequency is zero (or the input frequency of complete phase detector is identical with the setting of the filter). On the other hand, the behavior of phase detector in [34] is different. The maximal output DC voltage is available for the largest phase/frequency difference, zero voltage for alignment of the input and reference waves.…”