Compact Code Generation for Tightly-Coupled Processor Arrays

Boppu, Srinivas; Hannig, Frank; Teich, Jürgen

doi:10.1007/s11265-014-0891-2

Cited by 11 publications

(6 citation statements)

References 15 publications

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“…These conditions partition into the set of input variables in , the set of output variables out , and the set of internal variables var . 2 Furthermore, internal variables may only be indexed uniformly 3 : When defining an internal variable ∈ var , the matrix must be the identity matrix and the vector must be 0; when using an internal variable , ∈ var , then , must be the identity matrix. In the latter case, we call , the dependence vector of the uniform dependence between , and .…”

Section: Loops the Polyhedral Model And Reduced Dependence Graphsmentioning

confidence: 99%

“…Running example. Only edge 2 4 has [ 2 4 ] ≠ 0 and is therefore the only edge requiring a propagation channel; for example, [ 2 4 ] ← (pe ⊲ 0 , east ⊳ 0 , west ⊲ 0 , pe ⊳ 0 ). Consequently, the edge gets assigned registers reg write [ 2 4 ] ← od0 (from pe ⊲ 0 ) and reg read [ 2 4 ] ← id0 (from pe ⊳ 0 ).…”

Section: Routing Of Propagation Channelsmentioning

confidence: 99%

“…with ∈ {0, 1, −} such that these assignments do not overlap for any two outgoing edges. These assignments can, for example, be determined using binary decision diagrams [2]. From these assignments, for each node , we build partial control signals:…”

Section: Control Signal Allocationmentioning

confidence: 99%

“…This corresponds to the array single-assignment property 2. Any PLA may be transformed to allow for such a partitioning 3.…”

mentioning

confidence: 99%

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Symbolic Loop Compilation for Tightly Coupled Processor Arrays

Witterauf¹,

Walter²,

Hannig³

et al. 2021

Preprint

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Loop compilation for Tightly Coupled Processor Arrays (TCPAs), a class of massively parallel loop accelerators, entails solving NPhard problems, yet depends on the loop bounds and number of available processing elements (PEs), parameters known only at runtime because of dynamic resource management and input sizes. Therefore, this article proposes a two-phase approach called symbolic loop compilation: At compile time, the necessary NP-complete problems are solved and the solutions compiled into a space-efficient symbolic configuration. At runtime, a concrete configuration is generated from the symbolic configuration according to the parameters values. We show that the latter phase, called instantiation, runs in polynomial time with its most complex step, program instantiation, not depending on the number of PEs.As validation, we performed symbolic loop compilation on real-world loops and measured time and space requirements. Our experiments confirm that a symbolic configuration is space-efficient and suited for systems with little memory-often, a symbolic configuration is smaller than a single concrete configuration-and that program instantiation scales well with the number of PEs-for example, when instantiating a symbolic configuration of a matrix-matrix multiplication, the execution time is similar for 4 × 4 and 32 × 32 PEs. CCS Concepts: • Computer systems organization → Systolic arrays; Embedded and cyber-physical systems; • Software and its engineering → Compilers.

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Section: Loops the Polyhedral Model And Reduced Dependence Graphsmentioning

confidence: 99%

Section: Routing Of Propagation Channelsmentioning

confidence: 99%

Section: Control Signal Allocationmentioning

confidence: 99%

“…This corresponds to the array single-assignment property 2. Any PLA may be transformed to allow for such a partitioning 3.…”

mentioning

confidence: 99%

See 2 more Smart Citations

Symbolic Loop Compilation for Tightly Coupled Processor Arrays

Witterauf¹,

Walter²,

Hannig³

et al. 2021

Preprint

Self Cite

View full text Add to dashboard Cite

show abstract

“…Such (computationally intensive) applications are usually characterized by intensive loops and common use of arrays. Different architectural design solutions [6] were proposed to increase performance and reduce power consumption. These solutions include DSPs, GPUs, VLIWs, and ASIPs combined with a myriad of techniques, e.g., loop transformations, software pipelining, and compiler optimizations [2,24,26].…”

Section: Introductionmentioning

confidence: 99%

A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

Ferreira

Denver

Pereira

et al. 2015

J Sign Process Syst

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In the past years, many works have demonstrated the applicability of Coarse-Grained Reconfigurable Array (CGRA) accelerators to optimize loops by using software pipelining approaches. They are proven to be effective in reducing the total execution time of multimedia and signal processing applications. However, the run-time reconfigurability of CGRAs is hampered overheads introduced by the needed translation and mapping steps. In this work, we present a novel run-time translation technique for the modulo scheduling approach that can convert binary code onthe-fly to run on a CGRA. We propose a greedy approach, since the modulo scheduling for CGRA is an NP-complete problem. In addition to read-after-write dependencies, the dynamic modulo scheduling faces new challenges, such as register insertion to solve recurrence dependences and to balance the pipelining paths. Our results demonstrate that the greedy run-time algorithm can reach a near-optimal ILP rate, better than an off-line compiler approach for a 16-issue VLIW processor. The proposed mechanism ensures software compatibility as it supports different source ISAs. As proof of concept of scaling, a change in the memory bandwidth has been evaluated. In this analysis it is demonstrated R. Ferreira ( ) · W. Denver that when changing from one memory access per cycle to two memory accesses per cycle, the modulo scheduling algorithm is able to exploit this increase in memory bandwidth and enhance performance accordingly. Additionally, to measure area and performance, the proposed CGRA was prototyped on an FPGA. The area comparisons show that a crossbar CGRA (with 16 processing elements and including an 4-issue VLIW host processor) is only 1.11 × bigger than a standalone 8-issue VLIW softcore processor.

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Invasive Tightly Coupled Processor Arrays

Lari

2016

Computer Architecture and Design Methodologies

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Compact Code Generation for Tightly-Coupled Processor Arrays

Cited by 11 publications

References 15 publications

Symbolic Loop Compilation for Tightly Coupled Processor Arrays

Symbolic Loop Compilation for Tightly Coupled Processor Arrays

A Dynamic Modulo Scheduling with Binary Translation: Loop optimization with software compatibility

Invasive Tightly Coupled Processor Arrays

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