Compact 138-GHz amplifier with 18-dB peak gain and 27-GHz 3-dB bandwidth

This paper presents a low-power D-Band amplifier suitable for ultrahigh-speed wireless communications. The three-stage fully differential amplifier with capacitive neutralization is fabricated in 40 nm CMOS provided by TSMC. Measurement results show that the D-band amplifier obtains a peak gain of 9.6 dB over a -3 dB bandwidth from 138 GHz to 164.5 GHz. It exhibits an output 1 dB compression point (OP1dB) of 1.5 dbm at the center frequency of 150 GHz. The amplifier consumes a low power of 27.3 mW from a 0.7 V supply voltage while its core occupies a chip area of 0.06 mm2.

Section: Design Of D-band Amplifiermentioning

confidence: 99%

“…Comparison with previous published amplifiers operating in the similar frequency band Parameter MWCL'11[10] Elec. Let'11[11] APMC'13[12] RFIT'15[5] …”

mentioning

confidence: 99%

Low-Power D-Band CMOS Amplifier for Ultrahigh-Speed Wireless Communications

Vu¹,

Takano²,

Fujishima³

2018

“…The cross-view of a grounded coplanar wave-guide transmission line (GCPW-TL) is depicted in Fig. 3 [3]. The GCPW-TL with the characteristic impedance of 50 Ω (the 50 Ω GCPW-TL) is used for shunt and series stubs of the matching networks and for connecting to the input and output pads of the 60 GHz PA. Its signal line consists of the RDL layer with a width of 8 µm.…”

Section: Design Of 60 Ghz Power Amplifiermentioning

confidence: 99%

A 60 GHz CMOS Power Amplifier for Wireless Communications

Vu¹

2018

This paper presents a 60 GHz power amplifier (PA) suitable for wireless communications. The two-stage wideband PA is fabricated in 55 nm CMOS. Measurement results show that the PA obtains a peak gain of 16 dB over a -3 dB bandwidth from 57 GHz to 67 GHz. It archives an output 1 dB compression point (OP1dB) of 4 dbm and a peak power added efficiency (PAE) of 12.6%. The PA consumes a total DC power of 38.3 mW from a 1.2 V supply voltage while its core occupies a chip area of 0.45 mm2.

“…To realize cost-effective chips, area reduction is important. In order to reduce the area of the amplifier, we proposed the "fishbone layout" [7]. In this technique, GCPW-TL stubs used in matching networks are arranged regularly at narrow spacings, and the GCPW-TLs themselves are designed to be narrow, thereby reducing the footprint.…”

Section: Two-way D-band Power Amplifiermentioning

confidence: 99%

A 300 GHz CMOS Transmitter Front-End for Ultrahigh-Speed Wireless Communications

Vu¹,

Fujishima²

2017

This paper presents a 300 GHz transmitter front-end suitable for ultrahigh-speed wireless communications. The transmitter front-end realized in TSMC 40 nm CMOS consists of a common-source (CS) based doubler driven by a two-way D-band power amplifier (PA). Simulation results show that the two-way D-band PA obtains a peak gain of 21.6 dB over a -3 dB bandwidth from 132 GHz to 159 GHz. It exhibits a saturated power of 7.2 dBm and a power added efficiency (PAE) of 2.3%, all at 150 GHz. The CS based doubler results in an output power of 0.5 mW at 300 GHz. The transmitter front-end consumes a DC power of 205.8 mW from a 0.9 V supply voltage while it occupies an area of 2.1 mm2.