2020
DOI: 10.1142/s0129156420400133
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Compact 1-Bit Full Adder and 2-Bit SRAMs Using n-SWS-FETs

Abstract: This paper presents Spatial Wavefunction Switched (SWS)-FETs have been proposed to implement ternary and quaternary logic, 2-bit DRAM cells, and static random-access memories (SRAMs) in nMOS-SWS and CMOS-SWS configurations. This paper presents simulation of a 1-bit Full Adder using n-SWS-FETs. In addition, simulation of 2-bit SRAMs is presented for a quantum dot channel and a four quantum well nSWS-FET.SRAMs.

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“…A gold capping layer was added to the waveguides with copper cladding to avoid copper oxidation and facilitate wire bonding. The processed wafers were finally cleaved into 1-2-mm-long bars and indium-mounted onto copper blocks (Salama et al, 2021).…”
Section: Terahertz Plasmatic Collimator Design 4 Results and Discussionmentioning
confidence: 99%
“…A gold capping layer was added to the waveguides with copper cladding to avoid copper oxidation and facilitate wire bonding. The processed wafers were finally cleaved into 1-2-mm-long bars and indium-mounted onto copper blocks (Salama et al, 2021).…”
Section: Terahertz Plasmatic Collimator Design 4 Results and Discussionmentioning
confidence: 99%