Common-Centroid Capacitor Layout Generation Considering Device Matching and Parasitic Minimization

PACES: A Partition-Centering-Based Symmetry Placement for Binary-Weighted Unit Capacitor Arrays

“…The locations of UC's for all Ci's can be expressed as follows, C={(i, j)}, i=1~32, j=1~8; C9={(2i+1, 2j+1), (2i+2, 2j+2)}, i=0~15, j=0~7; C0={ (16,9)}; C1={ (17,8)}; C2={ (8*(2i+1)+1, 8*(2j+1)), \ (8*(2i+1)+16, 8*(2j+1)+1) }, i=0, j=0; C3={ (8*(2i+1), 4*(2j+1)+1), \ (8*(2i+1)+17, 4*(2j+1)) }, i=0, j=0~1; C4={ (4*(2i+1)+1, 4*(2j+1)), \ (4*(2i+1)+16, 4*(2j+1)+1) }, i=0~1, j=0~1; C5={ (4*(2i+1), 2*(2j+1)+1), \ (4*(2i+1)+17, 2*(2j+1)) }, i=0~1, j=0~3; C6={ (2*(2i+1)+1, 2*(2j+1)), \ (2*(2i+1)+16, 2*(2j+1)+1) }, i=0~3, j=0~3; C7={ (2*(2i+1), 2j+1), \ (2*(2i+1)+17, 2j+2) }, i=0~3, j=0~7; C8=C-C9-C7-C6-C5-C4-C3-C2-C1-C0; Fig. 11 shows the placement of this 9-bit binary-weighted PACES placement.…”

“…Capacitor mismatches can generally be classified as systematic or random mismatches. Numerous studies have applied techniques to unit capacitor placement such as common-centroid placement to alleviate systematic and random mismatches [4][5][6][7][8][9][10][11][12][13][14][15][16] and routing techniques such as length matching to reduce the effect of a parasitic mismatch [17][18][19].…”

“…Given the capacitance Ci,M, CCi, and CTP, the binary-weighted ratio R i,θ # with respect to θ=90 ○ is computed based on(17). Then,…”

Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC

“…Figure 1: A charge-scaling DAC (a) without routinginduced parasitic capacitors, and (b) with routinginduced parasitic capacitors. [6,12] According to [6,12], when designing the capacitor layout of a charge-scaling DAC, the accuracy of capacitance ratios correlates closely with the matching properties among the binary-weighted capacitors and the induced parasitics due to interconnecting wires. There are four kinds of routinginduced parasitic capacitors in a charge-scaling DAC, as shown in Figure 1 and C T S , may have great impact on the ratio of binary-weighted capacitors and the accuracy of a charge-scaling DAC.…”

“…They failed to consider the routing-induced parasitics which may destroy the resulting matching properties of ratioed capacitors even if the placement is perfectly matched. Only very few recent works [5,6,12] proposed automatic routing algorithms for wiring within a common-centroid unit capacitor array considering length-ratio matching [5] and parasitic minimization [6,12]. None of the previous works mentioned how to effectively minimize unit capacitor size, which depends on the matching quality of C T B i and C T S , such that both chip area and power consumption of a charge-scaling DAC can also be minimized.…”