Combining multiple DFT schemes with test generation

Mathew, B.; Saab, D.G.

doi:10.1109/43.766721

Cited by 4 publications

(2 citation statements)

References 44 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…All simulations and test generation were carried out on a Hewlett-Packard Linux workstation with a 2GHz dual-core Intel processor and 2GB RAM. Table 1 lists the trigger and Trojan coverage results for a set of combinational (ISCAS-85) and sequential (ISCAS-89) benchmarks using stuck-at ATPG patterns (generated using the algorithm in [7]), weighted random patterns and MERO test patterns. It also lists the number of total nodes in the circuit and the number of rare nodes identified by RO-Finder tool based on signal probability.…”

Section: Simulation Setupmentioning

confidence: 99%

MERO: A Statistical Approach for Hardware Trojan Detection

Chakraborty

Wolff

Sauseng

et al. 2009

Lecture Notes in Computer Science

310

154

View full text Add to dashboard Cite

Abstract. In order to ensure trusted in-field operation of integrated circuits, it is important to develop efficient low-cost techniques to detect malicious tampering (also referred to as Hardware Trojan) that causes undesired change in functional behavior. Conventional postmanufacturing testing, test generation algorithms and test coverage metrics cannot be readily extended to hardware Trojan detection. In this paper, we propose a test pattern generation technique based on multiple excitation of rare logic conditions at internal nodes. Such a statistical approach maximizes the probability of inserted Trojans getting triggered and detected by logic testing, while drastically reducing the number of vectors compared to a weighted random pattern based test generation. Moreover, the proposed test generation approach can be effective towards increasing the sensitivity of Trojan detection in existing side-channel approaches that monitor the impact of a Trojan circuit on power or current signature. Simulation results for a set of ISCAS benchmarks show that the proposed test generation approach can achieve comparable or better Trojan detection coverage with about 85% reduction in test length on average over random patterns.

show abstract

Section: Simulation Setupmentioning

confidence: 99%

MERO: A Statistical Approach for Hardware Trojan Detection

Chakraborty

Wolff

Sauseng

et al. 2009

Lecture Notes in Computer Science

310

154

View full text Add to dashboard Cite

show abstract

“…All previous methods [5, 6,9,13] combined partial reset, partial scan design and/or observation point insertion to derive satisfactory fault coverage because the previous partial reset methods (including observation point insertion) cannot obtain good fault coverage. The most important reason is that all partial reset flip-flops were not controlled by independent reset signals.…”

Section: Introductionmentioning

confidence: 99%

Partial reset for synchronous sequential circuits using almost independent reset signals

Xiang

Xu²

Proceedings 19th IEEE VLSI Test Symposium. VTS 2001

View full text Add to dashboard Cite

A flip-flop with a reset line makes it easily controllable and initializable, which can greatly reduce test generation time and test sequence length. A partial reset method combined with observation point insertion is presented for synchronous sequential circuits based on a testability measure with respect to iteratively calculated circuit state information and conflict analyses. Partial reset flip-flop selection according to a circuit-state-information-based measure and conflict analysis can break critical cycles of the circuit, make the circuit easy-to-initialize, and reduce potential conflicts in sequential ATPG. The most important reason why previous partial reset methods cannot completely improve testability is that partial reset flip-flops are not controlled by independent reset signals. Testability can be enhanced greatly when partial reset flipflops are judiciously controlled by independent reset lines. A new testability structure is proposed t o design a partial reset flip-flop, which makes the method economical in area, pin and delay overheads. It is demonstrated that a combination of partial reset and observation point insertion can be an attractive alternative to scan design, which presents at-speed test.

show abstract

Logic Testing for Hardware Trojan Detection

Govindan

Chakraborty

2017

The Hardware Trojan War

View full text Add to dashboard Cite

Combining multiple DFT schemes with test generation

Cited by 4 publications

References 44 publications

MERO: A Statistical Approach for Hardware Trojan Detection

MERO: A Statistical Approach for Hardware Trojan Detection

Partial reset for synchronous sequential circuits using almost independent reset signals

Logic Testing for Hardware Trojan Detection

Contact Info

Product

Resources

About