Combined MOS–IGBT–SCR Structure for a Compact High-Robustness ESD Power Clamp in Smart Power SOI Technology

Abstract

Smart power technologies are required to withstand high-electrostatic-discharge (ESD) robustness under both powered and unpowered conditions, particularly for automotive and aeronautic applications among many others. They are concurrently confronted to the challenges of high-temperature operation in order to reduce heat-sink-related costs. In this context, very compact high-robustness ESD protections with low sensitivity to temperature are required. To fulfill this need, we studied a new ESD protection structure that combines in the same component MOS, IGBT, and thyristor effects. This is achieved by inserting in the same LDMOS device P + diffusions in the drain. We studied the impact of N + /P + ratios on R ON and holding current at high temperatures. Structure optimization has been realized with 3-D TCAD simulation and experimentally validated. The proposed structures provide high ESD robustness with small footprint and reduced temperature sensitivity compared with classical solutions. Original design solutions to improve their immunity to latchup are also presented.

Optimization of a MOS–IGBT–SCR ESD protection component in smart power SOI technology

“…This choice can be explained by the fact that the obtained results in the previous silicon run exhibited the maximum and the minimum holding current for the 1P4N and 3P1N respectively, and the best ESD performance for the 1P2N. The results confirmed that the effect of P + diffusion percentage in the drain, corresponding to the IGBT one, has the same effect as shown and explained in [4].…”

“…After carrying out TCAD simulations using Sentaurus Device and based on previous results obtained in [3], [4], [10], three major topological modifications have been applied in order to make this component latch-up compliant:…”

“…The principal problem of this device is the control of the SCR triggering [6]- [9]. Results of the first two runs are discussed in [3], [4]. the minimum holding current of the SCR to avoid any latch-up is equal to 100 mA ( Fig.…”

“…Due to the significant improvement obtained with a channel w In a previous work [4], we proposed and studied several layout variations (different P + diffusion proportions in the drain, different configurations of the IGBT section in the drain and the reduction of the channel width). They resulted in a clear but insufficient experimental improvement of the holding current and voltage after triggering.…”

“…In a previous work, we proposed a new ESD component (MOS-IGBT-SCR) and improved it in order to increase ESD performance and improve the latch up immunity [3] [4]. ESD performance was excellent but margin to prevent latch up was not satisfying.…”