Combinational test generation for various classes of acyclic sequential circuits

Kim, Yong Chang; Agrawal, Vishwani D.; Saluja, Kewal K.

doi:10.1109/test.2001.966734

Cited by 8 publications

References 16 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

Reducibility of sequential test generation to combinational test generation for several delay fault models

Iwagaki

Ohtake

Fujiwara

2003

Proceedings of the 7th International Conference on Properties and Applications of Dielectric Materials (Cat No 03CH37417) ATS-0

View full text Add to dashboard Cite

This paper presents a new structure, called discontinuous reconvergence structure (DR-structure), of sequential circuits with easy testability for delay faults. We show that the delay fault test generation problem for sequential circuits with DR-structure can be reduced to that for their time-expansion models, which are combinational circuits. Based on the reducibility, we propose a test generation method for delay faults in sequential circuits with DRstructure. This method can be applied to several delay fault models. By some experiments, we show that the proposed method is effective in the hardware overhead, the test generation time and the fault efficiency.

show abstract

Reducibility of sequential test generation to combinational test generation for several delay fault models

Iwagaki

Ohtake

Fujiwara

2003

Proceedings of the 7th International Conference on Properties and Applications of Dielectric Materials (Cat No 03CH37417) ATS-0

View full text Add to dashboard Cite

show abstract

Acceleration of Transition Test Generation for Acyclic Sequential Circuits Utilizing Constrained Combinational Stuck-At Test Generation

Iwagaki

Ohtake

Fujiwara

European Test Symposium (ETS'05)

View full text Add to dashboard Cite

An extended class of sequential circuits with combinational test generation complexity

Inoue

Jinno

Fujiwara

Proceedings. IEEE International Conference on Computer Design: VLSI in Computers and Processors

View full text Add to dashboard Cite

We introduce a class of sequential circuits with internally switched balanced structure which allows test generation with combinational test generation complexity. The proposed class includes any other known classes with this feature. This paper also considers faults in hold registers and switches regarded as macros, while any related work does not consider faults in such macros. Experimental results show the effectiveness of using combinational test generation for the circuits with internally switched balanced structure.

show abstract

Combinational test generation for various classes of acyclic sequential circuits

Cited by 8 publications

References 16 publications

Reducibility of sequential test generation to combinational test generation for several delay fault models

Reducibility of sequential test generation to combinational test generation for several delay fault models

Acceleration of Transition Test Generation for Acyclic Sequential Circuits Utilizing Constrained Combinational Stuck-At Test Generation

An extended class of sequential circuits with combinational test generation complexity

Contact Info

Product

Resources

About