Coin Flipping PUF: A Novel PUF With Improved Resistance Against Machine Learning Attacks

Tanaka, Yūki; Bian, Song; Hiromoto, Masayuki; Satō, Takashi

doi:10.1109/tcsii.2018.2821267

Cited by 19 publications

(10 citation statements)

References 15 publications

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“…To provide a practical usage, the Arbiter PUF must take additional effort to obtain stable CRPs under different environment conditions. Some hardware-aided architectures, such as [16][17][18][19][20], also have a fatal weakness in being susceptible to environmental conditions.…”

Section: Related Workmentioning

confidence: 99%

“…Given l • i LUTs in the P D , we need to use 16 • l • i bits to model the P D in the initialize phase of proposed model. As a result, the attacker will take exponentially time complexity O(2 16•l•i ) to compromise the P D . In contrast, D cp of our model only costs linear time complexity when the P D and the matrix A are known in system.…”

Section: Brute-force Attacks To P Dmentioning

confidence: 99%

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STT-DPSA: Digital PUF-Based Secure Authentication Using STT-MRAM for the Internet of Things

et al. 2020

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Physical unclonable function (PUF), a hardware-efficient approach, has drawn a lot of attention in the security research community for exploiting the inevitable manufacturing variability of integrated circuits (IC) as the unique fingerprint of each IC. However, analog PUF is not robust and resistant to environmental conditions. In this paper, we propose a digital PUF-based secure authentication model using the emergent spin-transfer torque magnetic random-access memory (STT-MRAM) PUF (called STT-DPSA for short). STT-DPSA is an original secure identity authentication architecture for Internet of Things (IoT) devices to devise a computationally lightweight authentication architecture which is not susceptible to environmental conditions. Considering hardware security level or cell area, we alternatively build matrix multiplication or stochastic logic operation for our authentication model. To prove the feasibility of our model, the reliability of our PUF is validated via the working windows between temperature interval (−35 ∘ C, 110 ∘ C) and Vdd interval [0.95 V, 1.16 V] and STT-DPSA is implemented with parameters n = 32, i = o = 1024, k = 8, and l = 2 using FPGA design flow. Under this setting of parameters, an attacker needs to take time complexity O( 2 256 ) to compromise STT-DPSA. We also evaluate STT-DPSA using Synopsys design compiler with TSMC 0.18 um process.

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Section: Related Workmentioning

confidence: 99%

Section: Brute-force Attacks To P Dmentioning

confidence: 99%

STT-DPSA: Digital PUF-Based Secure Authentication Using STT-MRAM for the Internet of Things

et al. 2020

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“…Therefore, in recent efforts, special attention is paid to design PUFs that are resilient to ML attacks [1], [2]. In various cases, to show how the resiliency of a newly designed PUF is strengthened, an empirical ML algorithm (e.g., support vector machine, SVM, algorithms) is chosen and applied to the PUF.…”

Section: Introductionmentioning

confidence: 99%

PUFmeter a Property Testing Tool for Assessing the Robustness of Physically Unclonable Functions to Machine Learning Attacks

2019

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As PUFs become ubiquitous for commercial products (e.g., FPGAs from Xilinx, Altera, and Microsemi), attacks against these primitives are evolving toward more omnipresent and even advanced techniques. Machine learning (ML) attacks, among other non-invasive attacks, are proven to be feasible and cost-effective in the real-world. However, for PUF designers, it still remains an open question whether their countermeasures, or even new designs, are resistant to these types of attacks. Although standard metrics for estimating PUF quality exist, the most common approaches for measuring resistance to ML attacks are empirical. This paper introduces PUFmeter, a new publicly available toolbox consisting of in-house developed algorithms, to provide a firm basis for the robustness assessment of PUFs against ML attacks. To this end, new metrics and notions are reintroduced by PUFmeter to PUF designers and manufacturers. Furthermore, to prepare the PUF input-output pairs adequately before conducting any analysis, PUFmeter involves modules that output the minimum number of measurement repetitions and the upper bound on the noise level affecting the PUF responses.INDEX TERMS Physically unclonable functions, PUF circuit design, machine learning, property testing.

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“…[5,6]). These are the reasons why PUFs are drawing more and more attention in modern secure electronics-they can make it possible to create "a vault" for cryptographic keys, without building an actual vault [7,8].…”

Section: Introductionmentioning

confidence: 99%

“…The advantages and applications of PUFs initiated a search for methods of harvesting of PUF keys from physical processes. Among proposed solutions, we can find: ring oscillators [7,9], transient effect ring oscillators [10], dynamic ring oscillators [11], ordering-based ring oscillator [12], convergence time of bistable rings [8], sneak paths in the resistive X-point array [13], power consumption differences of Advanced Encryption Standard Sbox inversion functions [14], occurrence of metastability [15], static memory [16,17], dynamic memory [18,19], switching behavior of emerging magneto-resistive memory devices [20], switching of resistive random access memory [21], reduction-oxidation resistive switching memories [22], decay-based Dynamic Random Access Memory [23], locally enhanced defectivity [24], combination of multiplexers and arbiters [25], wireless sensors [26], Complementary Metal-Oxide Semiconductor image sensors [27], nonlinearities of data converters [28], mismatch of capacitor ratios [29], primitive shifting permutation network (barrel shifter) [30], cellular neural networks [31], customized dynamic two-stage comparator [32], and many others.…”

Section: Introductionmentioning

confidence: 99%

Chaos-Based Physical Unclonable Functions

Gołofit

Wieczorek

2019

Applied Sciences

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The concept presented in this paper fits into the current trend of highly secured hardware authentication designs utilizing Physically Unclonable Functions (PUFs) or Physical Obfuscated Keys (POKs). We propose an idea that the PUF cryptographic keys can be derived from a chaotic circuit. We point out that the chaos theory should be explored for the sake of PUFs as a natural mechanism of amplifying random process variations of digital circuits. We prove the idea based on a novel design of a chaotic circuit, which utilizes time in a feedback loop as an analog continuous variable in a purely digital system. Our design is small and simple, and therefore feasible to implement in inexpensive reprogrammable devices (not equipped with digital clock manager, programmable delay line, phase locked loop, RAM/ROM memory, etc.). Preliminary tests proved that the chaotic circuit PUFs work in both advanced Field-Programmable Gate Arrays (FPGAs) as well as simple Complex Programmable Logic Devices (CPLDs). We showed that different PUF challenges (slightly different implementations based on variations in elements placement and/or routing) have provided significantly different keys generated within one CPLD/FPGA device. On the other hand, the same PUF challenges used in a different CPLD/FPGA instance (programmed with precisely the same bit-stream resulting in exactly the same placement and routing) have enhanced differences between devices resulting in different cryptographic keys.

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Coin Flipping PUF: A Novel PUF With Improved Resistance Against Machine Learning Attacks

Cited by 19 publications

References 15 publications

STT-DPSA: Digital PUF-Based Secure Authentication Using STT-MRAM for the Internet of Things

STT-DPSA: Digital PUF-Based Secure Authentication Using STT-MRAM for the Internet of Things

PUFmeter a Property Testing Tool for Assessing the Robustness of Physically Unclonable Functions to Machine Learning Attacks

Chaos-Based Physical Unclonable Functions

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