Coefficients of thermal expansion of single crystalline β-Ga2O3 and in-plane thermal strain calculations of various materials combinations with β-Ga2O3

Abstract

The coefficients of thermal expansion (CTEs) of single crystalline, monoclinic β-Ga2O3 were determined by employing high-resolution X-ray diffraction measurements. This work reports the CTE measurements on a single crystalline β-Ga2O3 substrate. The CTE values along the “a,” “b,” and “c” axes are 3.77 × 10−6 °C−1, 7.80 × 10−6 °C−1, and 6.34 × 10−6 °C−1, respectively, and the CTE of the angle β (the angle between the “a” and “c” axes) is determined to be 1.31 × 10−4 ° K−1. All CTE values reported here are linear under the temperature regime between room temperature and 1000 °C. All measurements were performed in a controlled nitrogen gas environment, and no surface degradation was observed after these measurements. Thermal strain calculations with different material combinations involving β-Ga2O3 are also presented relevant to both epitaxial and wafer bonding applications for Si, InP, 3C–SiC, 6H–SiC, GaN, and sapphire.

Effect of H2O Molecules on Thermal Expansion of TiCo(CN)6

“…Positive thermal expansion (PTE) is a common phenomenon for most compounds in nature. Interestingly, there also exists the abnormal behavior of shrinking upon heating, namely, negative thermal expansion (NTE). − Thermal expansion is an important physical property for some functional materials, , so the presence of NTE behavior provides possible opportunities to controllable thermal expansion . Benefiting from the development of modern characterization technology, many NTE compounds have been discovered and new NTE mechanisms proposed in last 2 decades. − So far, mechanisms for most NTE compounds can be understood as either phonon- or electron-driven. , The phonon-driven NTE compounds have the typical crystal structural features of open frameworks such as ZrW 2 O 8 , ScF 3 , ScCo­(CN) 6 , and MOF-5 .…”

Vertical Field-Plated NiO/Ga2O3 Heterojunction Power Diodes

“…The outer frame Si area (with of 3.8 mm × 3.8 mm) without holes serve as a square anchor, which is not released by HF, with three Si ribbons (300 µm × 300 µm) connecting each of the four sides of the square anchor to the center Si membrane. Bulk Si [49] and β-Ga2O3 [50] have a large difference of thermal expansion coefficients. As the Si thickness is reduced, it can accommodate more mechanical strain [51] than a bulk substrate.…”

Ga2O3-on-SiC Composite Wafer for Thermal Management of Ultrawide Bandgap Electronics

“…The wafers were produced by slicing 750 μm-thick disks from an ingot and polishing them to achieve an epi-ready finish . This orientation was selected because it is favorable over the (2̅01) and (001) orientations due to the higher cross-plane thermal conductivity and lower coefficient of thermal expansion (CTE) mismatch with 4H-SiC . The surface of the 25 mm-diameter Ga 2 O 3 wafer was processed to result in an average surface roughness of ∼1 nm [root mean square (rms) roughness of 2.8 nm].…”

“…It should be noted that the stress/strain induced by the CTE mismatch of the two attached materials must be managed such that the heterointerface stays intact from room temperature up to high-temperature conditions associated with the subsequent device-processing steps. Although diamond possesses a higher thermal conductivity (>1500 W/m·K) than 4H-SiC, 4H-SiC was selected due to the availability of larger diameter semi-insulating substrates, high thermal conductivity (347 W/m·K), and lower CTE mismatch, , which would prevent debonding of Ga 2 O 3 caused by unacceptable levels of thermal strain at high growth temperatures, that is, 600–1000 °C for MBE, metalorganic chemical vapor deposition, and low-pressure chemical vapor deposition growth processes …”

“…13 This orientation was selected because it is favorable over the (2̅ 01) and (001) orientations due to the higher crossplane thermal conductivity 5 and lower coefficient of thermal expansion (CTE) mismatch with 4H-SiC. 14 The surface of the 25 mm-diameter Ga 2 O 3 wafer was processed to result in an average surface roughness of ∼1 nm [root mean square (rms) roughness of 2.8 nm]. This surface preparation was necessary to make the wafers suitable for the subsequent low-temperature bonding process.…”