Coefficient optimization for low power realization of FIR filters

Algorithms for low power and high speed FIR filter realization using differential coefficients

“…In the area of low power FIR filters earlier work investigated techniques like transforming the binary representation of FIR filter coefficients [2], [9] and perturbing the filter coefficients [7] for minimizing the computations needed for obtaining the filter output, while retaining the desired filter characteristics. Some other techniques that have been suggested are reordering the MAC sequence for minimizing the activities on the inputs of the computational units to decrease the power dissipated in them [1].…”

Low power FIR filter design using modified multi-objective artificial bee colony algorithm

“…For smaller order filters, minimizing both the PBR and SBR simultaneously is not possible. Similarly, filters which are optimized with regard to frequency domain characteristics consume more power and vice versa (Mehendale et al, 1995). The problem of meeting conflicting objectives can be tackled by using a Lagrange's multiplier which offers different weightages to the multiple objectives (Smith, 2002).…”

“…Power consumption in FIR filters can be minimized by reducing hardware complexity through filter implementation architecture (Arslan et al, 1996;Azarmehr and Ahmadi, 2012;Su et al, 1994;Mehendale et al, 1998;Hong et al, 2002;Xie et al, 2010) or by reducing switching activities between filter coefficients (Kavitha and Sasikumar, 2014;Najm, 1993;Nemani and Najm, 1996;Rahmeier et al, 2013;Shao et al, 2006) in their binary form, while processing through data buses of FPGA. In existing literature, Hamming distance (HD) between successive coefficients (Aktan et al, 2008;Gustafsson and Wanhammar, 2002;Mehendale et al, 1995;Merakos et al, 1997;Sankarayya et al, 1997) has been considered as a measure of switching activity. In other words, power consumption reduction in filter execution has been achieved by reducing the HD between the coefficients of the designed filter.…”

“…In other words, power consumption reduction in filter execution has been achieved by reducing the HD between the coefficients of the designed filter. The HD reduction algorithm presented in Mehendale et al (1995) uses coefficient scaling and perturbation with iterative steepest descent strategy. In Sankarayya et al (1997) an iterative coefficient optimization algorithm has been proposed for HD reduction.…”

Energy-Aware Loop Scheduling and Assignment for Multi-Core, Multi-Functional-Unit Architecture

“…In [21,22], an operand sharing scheduling technique is proposed to schedule the operation nodes with the same operands as closely as possible to reduce the switching activities on the functional units. In [23], a scheduling algorithm for optimizing coefficients of a FIR filter is proposed to minimize the switching activities on memory data bus and functional units. The above techniques are either based on single-FU architecture [19,21,[23][24][25] or a fixed schedule [4,9,20].…”