Algorithms for low power and high speed FIR filter realization using differential coefficients

Abstract

Most realizations of FIR filters use the coefficients directly to compute the convolution with the input data. We present a set of new algorithms for low power and high-speed realization of FIR filters. The algorithms use various orders of differences between coefficients for computing the convolution. Also the results of computations are stored and reused, thus requiring more storage and storage accesses. These techniques result in a reduction in the net computations necessary per convolution as compared to directly using the coefficients. It is shown analytically that this computational reduction at the cost of more storage can result in a lower net computational energy dissipated and an enhanced speed. These algorithms are applied to an example FIR filter to quantify the energy savings and speedup.

Energy-efficient Hardware Architecture and VLSI Implementation of a Polyphase Channelizer with Applications to Subband Adaptive Filtering

“…Figure 8 To reduce the computational complexity of FIR filters, differential coefficients method [12] was proposed. In this approach, by considering the differential coefficient c i -c j , the computation of P…”

“…Computation sharing differential coefficient (CSDC) method [11] is efficiently used to obtain low complexity parallel multiplierless implementation of FIR filters. The main idea of CSDC approach is to combine the strength of differential coefficient method [12] and subexpression sharing [13,14], which leads to significant power savings in polyphase filters implementation. In addition to the algorithmic/architectural level techniques, efficient circuit level techniques are also used for low power implementation of polyphase channelizer.…”

Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing

“…The justification for this estimate is that if the th bit in the coefficient is zero, then the transition activity in the th row of the array multiplier is reduced. In [34], a similar expression was employed in estimating the energy dissipation of a shift-add multiplier. Let be the two's complement representation of the coefficient .…”

“…Let be the input signal with the maximum value and mean squared value . Assuming that we employ bits to quantize and that the quantization noise is a uniformly distributed signal over the interval where , we obtain the quantization noise power as follows: (32) From (32), the SQNR (dB) can be obtained as dB (33) which can be further simplified to obtain dB dB (34) where PAR (dB) is the PAR at the input, and is defined as dB (35) For an equalizer, we can assume that an automatic gain control (AGC) block normalizes the input signal so that the input signal range matches that of the analogto-digital converter (ADC). The root mean square (rms) value can then be computed by taking the square root of the time average of the squared input signal.…”

Computation Sharing Programmable FIR Filter for Low-Power and High-Performance Applications

“…Using those techniques, the FIR filtering operation can be simplified to add and shift operations. Common subexpressions elimination [5], [6] and differential coefficients method [7], [8] also explore low-complexity design of FIR filters by minimizing the number of additions in filtering operations. However, most of the previous work has been limited to the design of FIR filters with fixed coefficients, allowing the hardware to be optimized only for a particular fixed coefficient set.…”