Coding guidelines for pipelined processors

Rymarczyk, James W.

doi:10.1145/800050.801821

Cited by 21 publications

(4 citation statements)

References 1 publication

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“…Some coding guidelines for assemblylanguage-level programming are described in [23]. These guidelines are intended to be applied by hand either by a compiler writer or when programming at the assembly-language level.…”

Section: Related Problemsmentioning

confidence: 99%

Postpass Code Optimization of Pipeline Constraints

Hennessy

Groß

1983

ACM Trans. Program. Lang. Syst.

224

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Pipeline interlocks are used in a pipelined architecture to prevent the execution of a machine instruction before its operands are available. An alternative to this complex piece of hardware is to rearrange the instructions at compile time to avoid pipeline interlocks. This problem is called code reorganization and is studied here. The basic problem of reorganization of machine-level instructions at compile time is shown to be NP-complete. A heuristic algorithm is proposed, and its properties and effectiveness are explored. Empirical data from MIPS, a VLSI processor design, are given. The impact of code reorganization techniques on the rest of a compiler system is discussed.

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Section: Related Problemsmentioning

confidence: 99%

Postpass Code Optimization of Pipeline Constraints

Hennessy

Groß

1983

ACM Trans. Program. Lang. Syst.

224

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“…Furthermore, the limited number of registers in those architectures made the use of aggressive scheduling rather unattractive. As a result, scheduling was viewed as rather peripheral to the compilation process, in contrast to the central position it occupied for VLIW processors and, to a lesser extent, for more highly pipelined processors [187,188,166]. Now, with superscalar processors growing in popularity, the importance of scheduling, as a core part of the compiler, is better appreciated and a good deal of activity has begun in this area [189][190][191][192][193], unfortunately, sometimes unaware of the large body of literature that already exists.…”

Section: Scheduling For Rise and Superscalar Processorsmentioning

confidence: 99%

Instruction-Level Parallel Processing: History, Overview, and Perspective

Rau

Fisher

1993

Instruction-Level Parallelism

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instruction-level parallelism, VLIW processors, superscalar processors, pipelining, multiple operation issue, speculative execution, scheduling, register allocation Instruction-level Parallelism CILP) is a family of processor and compiler design techniques that speed up execution by causing individual machine operations to execute in parallel. Although ILP has appeared in the highest performance uniprocessors for the past 30 years, the 1980s saw it become a much more significant force in computer design. Several systems were built, and sold commercially, which pushed ILP far beyond where it had been before, both in terms of the amount of ILP offered and in the central role ILP played in the design of the system. By the end of the decade, advanced microprocessor design at all major CPU manufacturers had incorporated ILP, and new techniques for ILP have become a popular topic at academic conferences. This article provides an overview and historical perspective of the field of ILP and its development over the past three decades.

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“…(3) Some of the performance loss caused by simple issue methods can be compensated for by instruction scheduling by the compiler or assembly language programmer [20]. Of course, this places a significantly greater burden on software.…”

Section: Design Issues For Pipelined Scalar Processorsmentioning

confidence: 99%

Decoupled access/execute computer architectures

Smith

1984

ACM Trans. Comput. Syst.

176

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An architecture for high-performance scalar computation is proposed and discussed. The main feature of the architecture is a high degree of decoupling between operand access and execution. This results in an implementation that has two separate instruction streams that communicate via architectural queues. Performance comparisons with a conventional scalar architecture are given, and these show that significant performance gains can be realized. Single-instruction-stream versions, both physical and conceptual, are discussed, with the primary goal of minimizing the differences with conventional architectures. This allows known compilation and programming techniques to be used. Finally, the problem of deadlock in a decoupled system is discussed, and a deadlock prevention method is given.

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Coding guidelines for pipelined processors

Cited by 21 publications

References 1 publication

Postpass Code Optimization of Pipeline Constraints

Postpass Code Optimization of Pipeline Constraints

Instruction-Level Parallel Processing: History, Overview, and Perspective

Decoupled access/execute computer architectures

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