CODEC for echo-canceling, full-rate ADSL modems

Hester, R.K.; Mukherjee, Somnath; Padgett, Daniel; Richardson, D.; Bright, W.; Sarraj, M.; Nabicht, J.T.; Agah, M.; Bellaouar, A.; Chaudhry, I.; Hellums, J.R.; Islam, Kaisarul; Loloee, A.; Tsay, C.-Y.; Westphal, G.H.

doi:10.1109/4.808922

Cited by 19 publications

(4 citation statements)

References 9 publications

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“…As a system, EQF has one layer of hierarchy, and five instances of a single component, the LNA circuit [20] of Fig. 5.…”

Section: Experimental Synthesis Resultsmentioning

confidence: 99%

“…We focus on the remote modem at the user's end. The CODEC is the interface between the modem's DSP core and the line itself; its architecture (from [20]) appears in Fig. 1.…”

Section: Overview Of Eqf Circuit Benchmarkmentioning

confidence: 99%

“…To counter the persistent criticism that analog design--especially design beyond basic cells--is intrinsically "too hard" to make synthesis practical, we present a case study of synthesis for one significant block, an equalizer/filter (EQF), in the frontend of a state-of-the-art CODEC for a full-rate ADSL modem introduced by Texas Instruments in [20] in 1999. This design is "aggressively custom" in the sense argued above: it uses neither routine system nor cell-level circuit topologies, and meets difficult analog performance goals.…”

Section: Introductionmentioning

confidence: 99%

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A case study of synthesis for industrial-scale analog IP

Phelps¹,

Krasnicki²,

Rutenbar³

et al. 2000

Proceedings of the 37th Conference on Design Automation - DAC '00

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A persistent criticism of analog synthesis techniques is that they cannot cope with the complexity of realistic industrial designs, especially system-level designs. We show how recent advances in simulation-based synthesis can be augmented, via appropriate macromodeling, to attack complex analog blocks. To support this claim, we resynthesize from scratch, in several different styles, a complex equalizer/filter block from the frontend of a commercial ADSL CODEC, and verify by full simulation that it matches its original design specifications. As a result, we argue that synthesis has significant potential in both custom and analog IP reuse scenarios.

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“…As a system, EQF has one layer of hierarchy, and five instances of a single component, the LNA circuit [20] of Fig. 5.…”

Section: Experimental Synthesis Resultsmentioning

confidence: 99%

“…We focus on the remote modem at the user's end. The CODEC is the interface between the modem's DSP core and the line itself; its architecture (from [20]) appears in Fig. 1.…”

Section: Overview Of Eqf Circuit Benchmarkmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

A case study of synthesis for industrial-scale analog IP

Phelps¹,

Krasnicki²,

Rutenbar³

et al. 2000

Proceedings of the 37th Conference on Design Automation - DAC '00

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show abstract

“…Data bandwidth can be located in the 3MHz to 29MHz interval and digitized or broadcast in analog format by the aforementioned transceiver. Various DSL front-end transceivers [3,4] implemented in CMOS have been reported. The transceiver presented in this paper is intended for home networking (HPNA for phone line, HomePlug for powerline), as well as for single carrier VDSL systems.…”

Section: Introductionmentioning

confidence: 99%

A 12-bit integrated analog front-end for broadband wireline networks

Mehr¹,

Maulik²,

Paterson³

Proceedings of the IEEE 2001 Custom Integrated Circuits Conference (Cat. No.01CH37169)

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An integrated transceiver for broadband wirelinenetworks is presented. The transceiver includes a receive data path, a transmit data path, and auxiliary functions including serial port interface, clock and reference generation blocks, and voltage regulator control circuitry. The receive data path provides constant input impedance and is composed of two variable gain amplifier (VGA) blocks, a n analog Q-pole filter, a 12-bit analog-to-digital converter ( A D C ) sampling at 32MHz, and a digital high-pass filter. The transmit data path contains digital interpolation filters and a 12-bit digital-to-analog converter (DAC) sampling at 128MHz. The chip was implemented in doublepoly triple-metal 0.35pm CMOS technology. Measured performance f o r both receive and transmit data paths meets target specifications with n o noticeable crosstalk. 7-2-1 0-7803-6591-7/01/$10.00 0 2001 IEEE IEEE 2001 CUSTOM INTEGRATED CIRCUITS CONFERENCE

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High Speed Digital-Analog Converters — The Dynamic Linearity Challenge

Bugeja

2003

Analog Circuit Design

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CODEC for echo-canceling, full-rate ADSL modems

Cited by 19 publications

References 9 publications

A case study of synthesis for industrial-scale analog IP

A case study of synthesis for industrial-scale analog IP

A 12-bit integrated analog front-end for broadband wireline networks

High Speed Digital-Analog Converters — The Dynamic Linearity Challenge

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