Code transformation and instruction set extension

Abstract

The demand for flexible embedded solutions and short time-to-market has led to the development of extensible processors that allow for customization through user-defined instruction set extensions (ISEs). These are usually identified from plain C sources. In this article, we propose a combined exploration of code transformations and ISE identification. The resulting performance of such a combination has been measured on two benchmark suites. Our results demonstrate that combined code transformations and ISEs can yield average performance improvements of 49%. This outperforms ISEs when applied in isolation, and in extreme cases yields a speed-up of 2.85.

Μεθοδολογίες Αυτοματοποιημένης Εξερεύνησης Και Σύνθεσης Επαναδιατάξιμων Συνεπεξεργαστών Υλικού

“…The exploration is performed at the granularity of the entire kernel, thus the impact of unrolling on the execution of primary operations is not investigated. Recently, the impact of the code's structure has been evaluated in the field of Application Specific Instruction Processor (ASIP) design for exposing more beneficial instruction extensions [13], [14]. These works concentrate on the instruction identification problem rather than the design space exploration problem for Pareto-optimal coprocessor instantiations which this work targets to.…”

“…Compiler-directed DSE (CompDirected) assumes two exploration loops, one for exploring code-level optimizations and another for exploring various resource allocation i.e. [9], [10], [11], [12], [13], [14].…”

“…(b) Compiler assisted with CLK selection exploration [6], [7], [8]. (c) Compiler directed exploration [9], [10], [11], [12], [13], [14]. (d) Proposed compiler-in-the-loop exploration.…”

“…At first, all the multiplication operations of the DFG are inserted in a list (line 4). Then the values of input edges for each multiplication operation in this list are checked, to determine the DepthFactor in each case (lines [5][6][7][8][9][10][11][12][13][14]. If one of the multiplication's input operands has a value smaller than V alue ≤ 15 then only one pipeline stage is needed for multiplication (lines 6-7).…”

“…For each operation, its parent nodes are stored in P arentOpList (line 10). If a parent node has been scheduled in the previous control step, then the index of the FPS unit, where the parent node was bound, is retrieved and the operation in the current control step (op i ) is mapped to the right adjacent pipeline stage through map(op i , index+1) (lines [11][12][13][14]. In case that none of the parent nodes is scheduled in the previous control step, the operation is mapped to the first available FPS unit (line 16).…”