Loop Nest Tiling for Image Processing and Communication Applications

Bielecki, Wlodzimierz; Palkowski, Marek

doi:10.1007/978-3-319-48429-7_28

Cited by 1 publication

(1 citation statement)

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“…Tiling is a vital technique to gain both data locality and coarse-grained parallelization of loop nests [23,24]. Parsa et al [25] presented a genetic algorithm (GA) to tile the iteration space of the nested loops with more than three dimensions.…”

Section: Relatedmentioning

confidence: 99%

PVL: Parallelization and Vectorization of Affine Perfectly Nested-Loops Considering Data Locality on Short-Vector Multicore Processors using Intrinsic Vectorization

Seyfari¹,

Lotfi²,

Karimpour³

2017

SCPE

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There is an urgent need for high-performance computations. Cores and Single Instruction Multiple Data (SIMD) units are important resources of modern architectures to speed up the execution of programs. Also, the importance of the data locality cannot be neglected in computations. Using cores, SIMD units, and data locality simultaneously is critical to gain peak performance of the architecture. But, there are a few research efforts trying to consider these three resources at the same time.There is a challenge in choosing loops which could be whether run on SIMD units or cores for vectorization and parallelization, respectively. This paper proposes an approach, named PVL, for parallelization and vectorization of nested loops considering data locality based on the polyhedral model on short-vector multicore processors. More precisely, PVL, tries to satisfy dependences in the middle levels of nested loop (the levels between outermost and innermost levels) while trying to move dependence-free loops to the outermost and innermost position in order to parallelize and vectorize them, respectively. The experimental results show that the proposed approach, PVL, is significantly effective compared to the other approaches.

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Section: Relatedmentioning

confidence: 99%