Code size reduction technique and implementation for software-pipelined DSP applications

Zhuge, Qingfeng; Xiao, Bin; Sha, Edwin H.-M.

doi:10.1145/950162.950168

Cited by 27 publications

(26 citation statements)

References 16 publications

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“…The code size is increased by introducing the prologue and epilogue after performing retiming. This problem can be solved by the code size reduction technique such as in [35].…”

Section: The Retiming Techniquementioning

confidence: 99%

Overhead-Aware System-Level Joint Energy and Performance Optimization for Streaming Applications on Multiprocessor Systems-on-Chip

Liu

Shao

Wang

et al. 2008

2008 Euromicro Conference on Real-Time Systems

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In this paper, we focus on joint energy and performance optimization for streaming applications on multiprocessor Systems-on-Chip by combining task-level coarse-grained software pipelining with DVS (Dynamic Voltage Scaling) and DPM (Dynamic Power Management) techniques with the considerations of transition overhead, inter-processor communication and discrete voltage levels. We propose a two-phase approach to solve the problem. In the first phase, we propose a coarse-grained task parallelization algorithm called RDAG to transform a periodic dependent task graph into a set of independent tasks based on the retiming technique [19]. In the second phase, we propose a novel scheduling algorithm called SpringS that works like a spring by iteratively adjusting task scheduling and voltage selection by combining DVS and DPM. We conduct experiments with a set of benchmarks from E3S [10] and TGFF [27]. The experimental results show that our technique can achieve 49.8% energy saving on average compared with the approach in [20], that applied DVS and DPM without software pipelining. In addition, given a tight timing constraint, our technique can obtain a feasible solution while the approach in [20] cannot.

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“…The code size is increased by introducing the prologue and epilogue after performing retiming. This problem can be solved by the code size reduction technique such as in [35].…”

Section: The Retiming Techniquementioning

confidence: 99%

Overhead-Aware System-Level Joint Energy and Performance Optimization for Streaming Applications on Multiprocessor Systems-on-Chip

Liu

Shao

Wang

et al. 2008

2008 Euromicro Conference on Real-Time Systems

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“…Code size reduction can be generally applied to any processors with or without predicate registers, and achieves smaller code size. For the details, please refer to the work published in [25].…”

Section: ¢£ ( ' )mentioning

confidence: 99%

Design optimization and space minimization considering timing and code size via retiming and unfolding

Zhuge

Xue

Shao

et al. 2006

Microprocessors and Microsystems

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The increasingly complicated DSP processors and applications with strict timing and code size constraints require design automation tools to consider multiple optimizations such as software pipelining and loop unfolding, and their effects on multiple design parameters. This paper presents an Integrated Framework for Design Optimization and Space Minimization (IDOM) toward finding the minimum configuration satisfying timing and code size constraints. We show an effective way to reduce the design space to be explored through the study of the fundamental properties and relationships among retiming function, unfolding factor, timing, and code size. We present theorems to show that a small set of feasible unfolding factors can be obtained effectively to produce high-quality designs. The IDOM algorithm is proposed to generate a minimal configuration of the design by integrating software pipelining, unfolding, and code size reduction techniques. The experimental results on a set of DSP benchmarks show the efficiency and effectiveness of our technique.

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“…From the results of the first phase, a basic candidate solution set I b ={3,5,7,8} is obtained from the candidate loop body by reselectable instruction map table. The basic candidate solutions generate a set of solution space {φ, 3, 5, 7, 8, (3,5), (3,7), (3,8), (5,7), (5,8), (7,8), (3,5,7), (3,5,8), (3,7,8), (5,7,8), (3,5,7,8)}. But, the branch and bound procedure discards the element 3 and 8 by heuristically chosen lower bound ,which we used 0.5, because those elements does not contribute an optimum solution.…”

Section: Phase 2: Branch and Bound Solution Search Strategymentioning

confidence: 99%

“…By carefully applying the preprocessing to the mission critical loops with profiling, the overall code size increase can be moderated. In addition, we recognize a research on code size reduction technique for software-pipelined loops [7]. The reported solution is based on a novel retiming function to reduce prologue and epilogue code sections with predication.…”

Section: Descriptionmentioning

confidence: 99%

Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs

Cho

Ayyagari

et al. 2006

Emerging Directions in Embedded and Ubiquitous Computing

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Abstract. An iterative modulo scheduling is very important for compilers targeting high performance multi-issue digital signal processors. This is because these processors are often severely limited by idle state functional units and thus the reduced idle units can have a positively significant impact on their performance. However, complex instructions, which are used in most recent DSPs such as mac, usually increase data dependence complexity, and such complex dependencies that exist in signal processing applications often restrict modulo scheduling freedom and therefore, become a limiting factor of the iterative modulo scheduler.In this work, we propose a technique that efficiently reselects instructions of an application loop code considering dependence complexity, which directly resolve the dependence constraint. That is specifically featured for accelerating software pipelining performance by minimizing length of intrinsic cyclic dependencies. To take advantage of this feature, few existing compilers support a loop unrolling based dependence relaxing technique, but only use them for some limited cases. This is mainly because the loop unrolling typically occurs an overhead of huge code size increment, and the iterative modulo scheduling with relaxed dependence techniques for general cases is an NP-hard problem that necessitates complex assignments of registers and functional units. Our technique uses a heuristic to efficiently handle this problem in pre-stage of iterative modulo scheduling without loop unrolling.

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Code size reduction technique and implementation for software-pipelined DSP applications

Cited by 27 publications

References 16 publications

Overhead-Aware System-Level Joint Energy and Performance Optimization for Streaming Applications on Multiprocessor Systems-on-Chip

Overhead-Aware System-Level Joint Energy and Performance Optimization for Streaming Applications on Multiprocessor Systems-on-Chip

Design optimization and space minimization considering timing and code size via retiming and unfolding

Instruction Re-selection for Iterative Modulo Scheduling on High Performance Multi-issue DSPs

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