Optimistic coalescing has been proven as an elegant and effective technique that provides better chances of safely coloring more registers in register allocation than other coalescing techniques. Its algorithm originally assumes homogeneous registers, which are all gathered in the same register file. Although this register architecture is still common in most general-purpose processors, embedded processors often contain heterogeneous registers, which are scattered in physically different register files dedicated for each dissimilar purpose and use. In this work, we show that optimistic coalescing is also useful for an embedded processor to better handle such heterogeneity of the register architecture, and developed a modified algorithm for optimal coalescing that helps a register allocator. In the experiment, an existing register allocator was able to achieve up to 13.0% reduction in code size through our coalescing, and avoid many spills that would have been generated without our scheme.
Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors-Code generation, compiler and optimizationGeneral Terms: Algorithms, Performance, Design, Experimentation Additional Key Words and Phrases: Register allocation, register coalescing, compiler, embedded processors, heterogeneous register architecture Part of this work was published in LCTES 2007. New contributions added to this article include Section 4.3, which describes the coloring heuristic which was applied to our modified optimistic coalescing; Sections 4.4 and 4.5, which propose two new techniques for further reducing spills in our modified optimistic coalescing; and Section 5, which extensively analyzes the impact of our coalescing technique with fuller benchmark codes.