Fast memory bank assignment for fixed-point digital signal processors

Abstract

Most vendors of digital signal processors (DSPs) support a Harvard architecture, which has two or more memory buses, one for program and one or more for data and allow the processor to access multiple words of data from memory in a single instruction cycle. Also, many existing fixed-point DSPs are known to have an irregular architecture with heterogeneous registers, which contains multiple register files that are distributed and dedicated to different sets of instructions. Although there have been several studies conducted to efficiently assign data to multimemory banks, most of them assumed processors with relatively simple, homogeneous general-purpose registers. Thus, several vendor-provided compilers for DSPs that we examined were unable to efficiently assign data to multiple data memory banks, thereby often failing to generate highly optimized code for their machines. As a consequence, programmers for these DSPs often manually assign program variables to memories so as to fully utilize multimemory banks in their code. This paper reports on our recent attempt to address this problem by presenting an algorithm that helps the compiler to efficiently assign data to multimemory banks. Our algorithm differs from previous work in that it assigns variables to memory banks in separate, decoupled code generation phases, instead of a single, tightly coupled phase. The experimental results have revealed that our decoupled algorithm greatly simplifies our code generation process; thus our compiler runs extremely fast, yet generates target code that is comparable in quality to the code generated by a coupled approach.

Run-Time Memory Optimization for DDMB Architecture Through a CCB Algorithm

“…However, their approach as well as the above ILP-based one has a drawback that the compilation time may increase substantially for large applications. To reduce compilation time, we proposed in [2] a fast approach based on a maximum spanning tree algorithm to solve multiple memory bank assignment in polynomial time.…”

“…Note that this on-chip memory is small and therefore, the efficient use of memory turns out to be the major challenge in DSP software development process. To partially address this issue, we developed a compiler strategy that assigns variables to multiple data memory banks such that overall system performance can be improved; Refer [2] for a detailed introduction. However, recent compiler validation efforts lead us to observe that even with our previous compiler techniques; The lack of an efficient compiler strategy, which can manage the runtime environment for variables in dual data memory banks, significantly hurts the overall DSP system performance.…”

“…Our experiment reveals that this scheme greatly helps the compiler to balance the total amount of memory space for ARs stored in the DDMBs, thus better utilizing the on-chip SRAM of the DSP, which in turn helps us to maximize the performance on our target DDMB architecture. For this work, we first apply our dual memory bank assignment technique [2] to assign local variables in a procedure into two ARs for the procedure, each of which must be stored in either memory bank X or Y, respectively. Then, as will be shown later, our scheme attempts to store the ARs such that both the banks are equally utilized and the amount of wasted memory space is minimized.…”

An Array Allocation Scheme for Energy Reduction in Partitioned Memory Architectures

“…e ij * c ij (4) subject to Equations 1, 2 and 3. Note that c ij s in the objective function are constants.…”

“…Assignment of variables to memory banks is also dealt with in [4]. Their work tries to optimize the assignment mainly for Digital Signal Processors.…”