Code Coverage of Assertions Using RTL Source Code Analysis

Athavale, Viraj; Ma, Sai; Hertz, Samuel; Vasudevan, Shobha

doi:10.1145/2593069.2593108

Cited by 13 publications

(2 citation statements)

References 6 publications

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“…Recent eforts [33,105] also use the code coverage as a metric to identify whether the number of assertions are enough. Athavale et al [13] deines a correctness based coverage metric. This work uses a combination of static and dynamic RTL code analysis to identify the covered RTL statements.…”

Section: Behaviors Generationmentioning

confidence: 99%

A Survey on Assertion-based Hardware Verification

et al. 2022

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Hardware verification of modern electronic systems has been identified as a major bottleneck due to the increasing complexity and time-to-market constraints. One of the major objectives in hardware verification is to drastically reduce the validation and debug time without sacrificing the design quality. Assertion-based verification is a promising avenue for efficient hardware validation and debug. In this paper, we provide a comprehensive survey of recent progress in assertion-based hardware verification. Specifically, we outline how to define assertions using temporal logic to specify expected behaviors in different abstraction levels. Next, we describe state-of-the art approaches for automated generation of assertions. We also discuss test generation techniques for activating assertions to ensure that the generated assertions are valid. Finally, we present both pre-silicon and post-silicon assertion-based validation approaches that utilize simulation, formal methods as well as hybrid techniques. We conclude with a discussion on utilizing assertions for verifying both functional and non-functional requirements.

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Section: Behaviors Generationmentioning

confidence: 99%

A Survey on Assertion-based Hardware Verification

et al. 2022

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“…Transformations of the behavioral RTL FSMD model are proposed in [19] in order to deal with false negative results of the equivalence checking of state sequences from conditional paths in equivalent checking. Static and dynamic analysis of the RTL source code is exercised in [20] to define and compute code coverage of assertions in the RTL code. Simulation-based verification is executed in [21] with generated scenario-based stimuli which are triggered in various ways.…”

Section: Wwwetasrcom Dossis: High-level Synthesis Integrated Verifica...mentioning

confidence: 99%

High-level Synthesis Integrated Verification

Dossis¹

2015

Eng. Technol. Appl. Sci. Res.

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It is widely known in the engineering community that more than 60% of the IC design project time is spent on verification. For the very complex contemporary chips, this may prove prohibitive for the IC to arrive at the correct time in the market and therefore, valuable sales share may be lost by the developing industry. This problem is deteriorated by the fact that most of conventional verification flows are highly repetitive and a great proportion of the project time is spent on last-moment simulations. In this paper we present an integrated approach to rapid, high-level verification, exploiting the advantages of a formal High-level Synthesis tool, developed by the author. Verification in this work is supported at 3 levels: high-level program code, RTL simulation and rapid, generated C testbench execution. This paper is supported by strong experimental work with 3-4 popular design synthesis and verification that proves the principles of our methodology.

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