Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273)
DOI: 10.1109/iccd.1998.727106
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Code coalescing unit: a mechanism to facilitate load store data communication

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Cited by 2 publications
(1 citation statement)
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“…A small level-0 data cache (L 0 ) [25], a different form of small buffer [12], or a L 0 only for critical loads [19] helps to reduce the load latency. However, since access to the L 0 requires going through normal pipeline stages to decode and generate addresses, it usually cannot achieve 0-cycle loads.…”
Section: Related Workmentioning
confidence: 99%
“…A small level-0 data cache (L 0 ) [25], a different form of small buffer [12], or a L 0 only for critical loads [19] helps to reduce the load latency. However, since access to the L 0 requires going through normal pipeline stages to decode and generate addresses, it usually cannot achieve 0-cycle loads.…”
Section: Related Workmentioning
confidence: 99%