Co-Design Flow for Embedded Systems (MPSoC)

Abstract

In this chapter, the authors explore the estimation of the performances in an earlier stage of (multi-processors system on chip) MPSoC design in which it is necessary to drive design space exploration and support important design decisions. Therefore, they address the co-design hardware/software with estimating performances in order to find an adequate solution, which consists in mapping the application on the components of architecture with respect the criteria of performance of the system defined from the beginning. The chapter provides a hybrid model for estimating performance in which cohabited simulation and analytical techniques are carried out via a link layer in order to reach an optimal architectural solution quickly. Thus, it allows faster performance estimation with better accuracy at different levels of abstraction.